LSM6DSM Datasheet, PDF(39/113 Page) STMicroelectronics – always-on 3D accelerometer and 3D gyroscope

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LSM6DSM Datasheet, PDF (39/113 Pages) STMicroelectronics – always-on 3D accelerometer and 3D gyroscope

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LSM6DSM

Digital interfaces

The Slave ADdress (SAD) associated to the LSM6DSM is 110101xb. The SDO/SA0 pin can

be used to modify the less significant bit of the device address. If the SDO/SA0 pin is

connected to the supply voltage, LSb is â1â (address 1101011b); else if the SDO/SA0 pin is

connected to ground, the LSb value is â0â (address 1101010b). This solution permits to

connect and address two different inertial modules to the same I2C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver

which has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LSM6DSM behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.

The increment of the address is configured by the CTRL3_C (12h) (IF_INC).

The slave address is completed with a Read/Write bit. If the bit is â1â (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is â0â (Write)

the master will transmit to the slave with direction unchanged. Table 13 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Command

Read

Write

Read

Write

SAD[6:1]

110101

Table 13. SAD+Read/Write patterns

SAD[0] = SA0

R/W

SAD+R/W

11010101 (D5h)

11010100 (D4h)

11010111 (D7h)

11010110 (D6h)

Table 14. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 15. Transfer when master is writing multiple bytes to slave

Master ST SAD + W

SUB

DATA

Slave

SAK

Table 16. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

SAK DATA

Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

NMAK SP

Slave

SAK

SAK DATA

DAT

DATA

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