LSM6DSM Datasheet, PDF (38/113 Pages) STMicroelectronics – always-on 3D accelerometer and 3D gyroscope

Digital interfaces
LSM6DSM
6.3
Auxiliary SPI
If LSM6DSM is configured in Mode3, the auxiliary SPI is available. The auxiliary SPI
interface is mapped in the following dedicated pins.
Pin name
OCS_Aux
SDx
SCx
SDO_Aux
Table 11. Auxiliary SPI pin details
Pin description
Auxiliary SPI 3/4-wire enable
Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)
Auxiliary SPI 3/4-wire interface serial port clock
SPI serial data
6.4
6.4.1
I²C serial interface
The LSM6DSM I²C is a bus slave. The I²C is employed to write the data to the registers,
whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Term
Transmitter
Receiver
Master
Slave
Table 12. I²C terminology
Description
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both the lines are high.
The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the
standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
38/113
DocID028165 Rev 2