K4R881869M Datasheet, PDF (61/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Glossary of Terms
ACT
activate
adjacent
ASYM
ATTN
ATTNR
ATTNW
AV
bank
BC
BBIT
broadcast
BR
bubble
BYT
BX
C
CAL
CBIT
CCA
CCB
CFM,CFMN
Channel
CLRR
CMD
CNFGA
CNFGB
COL
COL
COLC
COLM
column
command
COLX
Activate command from AV field.
To access a row and place in sense amp.
Two RDRAM banks which share sense
amps (also called doubled banks).
CCA register field for RSL V_OL/V_OH.
Power state - ready for ROW/COL
packets.
Power state - transmitting Q packets.
Power state - receiving D packets.
Opcode field in ROW packets.
A block of 2^RBIT•2 ^CBITstorage cells in the
core of the RDRAM.
Bank address field in COLC packet.
CNFGA register field - # bank address
bits.
An operation executed by all RDRAMs.
Bank address field in ROW packets.
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
CNFGB register field - 8/9 bits per byte.
Bank address field in COLX packet.
Column address field in COLC packet.
Calibrate (I_OL) command in XOP field.
CNFGB register field - # column address
bits.
Control register - current control A.
Control register - current control B.
Clock pins for receiving packets.
ROW/COL/DQ pins and external wires.
Clear reset command from SOP field.
CMOS pin for initialization/power control.
Control register with configuration fields.
Control register with configuration fields.
Pins for column-access control.
COLC,COLM,COLX packet on COL pins.
Column operation packet on COL pins.
Write mask packet on COL pins.
Rows in a bank or activated row in sense
amps have 2^CBIT dualocts column storage.
A decoded bit-combination from a field.
Extended operation packet on COL pins.
controller
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
COP
Column opcode field in COLC packet.
core
The banks and sense amps of an RDRAM.
CTM,CTMN Clock pins for transmitting packets.
current control Periodic operations to update the proper
I_OL value of RSL output drivers.
D
Write data packet on DQ pins.
DBL
CNFGB register field - doubled-bank.
DC
Device address field in COLC packet.
device
An RDRAM on a Channel.
DEVID
Control register with device address that is
matched against DR, DC, and DX fields.
DM
Device match for ROW packet decode.
doubled-bank RDRAM with shared sense amp.
DQ
DQA and DQB pins.
DQA
Pins for data byte A.
DQB
Pins for data byte B.
DQS
NAPX register field - PDN/NAP exit.
DR,DR4T,DR4F Device address field and packet framing
fields in ROWA and ROWR packets.
dualoct
16 bytes - the smallest addressable datum.
DX
Device address field in COLX packet.
field
A collection of bits in a packet.
INIT
Control register with initialization fields.
initialization Configuring a Channel of RDRAMs so
they are ready to respond to transactions.
LSR
CNFGA register field - low-power self-
refresh.
M
Mask opcode field (COLM/COLX packet).
MA
Field in COLM packet for masking byte A.
MB
Field in COLM packet for masking byte B.
MSK
Mask command in M field.
MVER
Control register - manufacturer ID.
NAP
Power state - needs SCK/CMD wakeup.
NAPR
Nap command in ROP field.
NAPRC
Conditional nap command in ROP field.
NAPXA
NAPX register field - NAP exit delay A.
NAPXB
NAPX register field - NAP exit delay B.
NOCOP
No-operation command in COP field.
NOROP
No-operation command in ROP field.
Page 59
Rev. 0.9 Jan. 2000