K4R881869M Datasheet, PDF (15/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
ROW-to-ROW Interaction - contin-
ued
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, t_PP
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the t_PP restriction.
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval t_RCDELAY which
depends upon the packet contents. Table 11 summarizes the
t_RCDELAY values for all possible cases. Note that if the COL
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T
CTM/CFM
ROW2
..ROW0
ROPa a0
t_RCDELAY
COL4
..COL0
COPb b1
DQA8..0
DQB8..0
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
Figure 7: ROW-to-COL Packet Interaction- Timing
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.
Table 11: ROW-to-COL Packet Interaction - Rules
Case # ROPa Da Ba Ra COPb
RC1 ACT Da Ba Ra NOCOP,RD,retire
RC2 ACT Da Ba Ra NOCOP
RC3 ACT Da Ba Ra RD,retire
RC4 ACT Da Ba Ra RD,retire
RC5 ACT Da Ba Ra RD,retire
RC6 PRER Da Ba Ra NOCOP,RD,retire
RC7 PRER Da Ba Ra NOCOP
RC8 PRER Da Ba Ra RD,retire
RC9 PRER Da Ba Ra RD,retire
Db
/= Da
== Da
== Da
== Da
== Da
/= Da
== Da
== Da
== Da
Bb
Cb1 t_RCDELAY
xxxx
x..x 0
xxxx
x..x 0
/= {Ba,Ba+1,Ba-1} x..x 0
== {Ba+1,Ba-1} x..x Illegal
== Ba
xxxx
x..x t_RCD
x..x 0
xxxx
x..x 0
/= {Ba,Ba+1,Ba-1} x..x 0
== {Ba+1,Ba-1} x..x Illegal
Example
Figure 15
Page 13
Rev. 0.9 Jan. 2000