K4R881869M Datasheet, PDF (38/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Control Register: TPARM
Address: 048₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0TCD0LY00 TCLS TCAS
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t_CAS-C core parameter in
t_CYCLE units. This should be “10” (2•t _CYCLE).
TCLS1..0 - Specifies the t_CLS-C core parameter in
t_CYCLE units. Should be “10” (2•t _CYCLE).
TCDLY0 - Specifies the t_CDLY0-C core parameter in
t_CYCLE units. This adds a programmable delay to Q
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “011” (3•t_CYCLE) through “101”
(5•t _CYCLE).
.
The equations relating the core parameters to the
datasheet parameters follow:
t_CAS-C = 2•t _CYCLE
t_CLS-C = 2•t _CYCLE
t_CPS-C = 1•t _CYCLE
Not programmable
t_OFFP = t_CPS-C + t_CAS-C + t_CLS-C - 1•t _CYCLE
= 4•t_CYCLE
t_RCD = t_RCD-C + 1•t _CYCLE - t_CLS-C
= t_RCD-C - 1•t _CYCLE
t_CAC = 3•t _CYCLE + t_CLS-C + t_CDLY0-C + t_CDLY1-C
(see table below for programming ranges)
TCDLY0 t_CDLY0-C TCDLY1 t_CDLY1-C
011
3•t _CYCLE
000
0•t_CYCLE
011
3•t _CYCLE
001
1•t_CYCLE
011
3•t _CYCLE
010
2•t_CYCLE
100
4•t _CYCLE
010
2•t_CYCLE
101
5•t _CYCLE
010
2•t_CYCLE
t_CAC
8•t_CYCLE
9•t_CYCLE
10•t_CYCLE
11•t_CYCLE
12•t_CYCLE
Figure 39: TPARM Register
Control Register: TFRM
Address: 049₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000000000000
TFRM3..0
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t_CYCLE units. This value must be greater than or
equal to the t_FRM,MIN parameter. This is the minimum
offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7•t _CYCLE) through
“1010” (10•t _CYCLE). TFRM is usually set to the value
which matches the largest t_RCD,MIN parameter (modulo
4•t _CYCLE) that is present in an RDRAM in the memory
system. Thus, if an RDRAM with t_RCD,MIN = 9•t_CYCLE
were present, then TFRM would be programmed to
5•t_CYCLE.
Figure 40: TFRM Register
Control Register: TCDLY1
Address: 04a₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0TCDLY1
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t_CDLY1-C core
parameter in t_CYCLE units. This adds a programmable
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0•t _CYCLE) through
“010” (2•t _CYCLE). Refer to Figure 39 for more details.
Figure 41: TRDLY Register
Page 36
Rev. 0.9 Jan. 2000