K4R881869M Datasheet, PDF(13/64 Page) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R881869M Datasheet, PDF (13/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R881869M

Preliminary

Direct RDRAMâ¢

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47

CTM/CFM

ROW2

..ROW0

ACT a0

COL4

..COL0

DQA8..0

DQB8..0

Transaction a: WR

WR a1

tRTR

retire (a1)

MSK (a1)

tCWD

D (a1)

PRER a2

ACT b0

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a3 = {Da,Ba}

COLM Packet

D Packet

T17

T18

T19

T20

T19

T20

T21

T22

CTM/CFM

COL4

COL3

COL2

COL1

COL0

MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

DQB8

DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71

DQB7

DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70

DQB1

DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64

DQB0

DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63

When M=1, the MA and MB

fields control writing of

individual data bytes.

When M=0, all data bytes are

written unconditionally.

Each bit of the MB7..MB0 field

controls writing (=1) or no writing

(=0) of the indicated DB bits when

the M bit of the COLM packet is one.

DQA8

MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7

DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA71

DQA7 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70

DQA1 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64

Each bit of the MA7..MA0 field

controls writing (=1) or no writing

(=0) of the indicated DA bits when

the M bit of the COLM packet is one.

DQA0

DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63

MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7

Figure 5: Mapping Between COLM Packet and D Packet for WR Command

Page 11

Rev. 0.9 Jan. 2000

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