K4R881869M Datasheet, PDF (46/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Electrical Conditions
Table 18: Electrical Conditions
Symbol
Parameter and Conditions
T_J
V_DD, V_DDA
V_DD,N, V_DDA,N
v_DD,N, v_DDA,N
V_CMOS
V_TERM
V_REF
V_DIL
V_DIH
V_DIS
A_DI
V_X
V_CM
V_CIS,CTM
V_CIS,CFM
V_IL,CMOS
V_IH,CMOS
Junction temperature under bias
Supply voltage
Supply voltage droop (DC) during NAP interval (t_NLIMIT)
Supply voltage ripple (AC) during NAP interval (t_NLIMIT)
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
Termination voltage
Reference voltage
RSL data input - low voltage
RSL data input - high voltage
RSL data input swing: V_DIS = V_DIH - V_DIL
RSL data asymmetry: A_DI = [(V_DIH - V_REF) + (V_DIL - V_REF)]/V_DIS
RSL clock input - crossing point of true and complement signals
RSL clock input - common mode V_CM = (V_CIH+V_CIL)/2
RSL clock input swing: V_CIS = V_CIH - V_CIL (CTM,CTMN pins).
RSL clock input swing: V_CIS = V_CIH - V_CIL (CFM,CFMN pins).
CMOS input low voltage
CMOS input high voltage
Timing Conditions
Min
-
2.50 - 0.13
-
-2.0
2.50 - 0.13
1.80 - 0.1
1.80 - 0.1
1.40 - 0.2
V_REF - 0.5
V_REF + 0.2
0.4
0
1.3
1.4
0.35
0.125
- 0.3
V_CMOS/2 + 0.25
Max
100
2.50 + 0.13
2.0
2.0
2.50 + 0.25
1.80 + 0.2
1.80 + 0.1
1.40 + 0.2
V_REF - 0.2
V_REF + 0.5
1.0
-20
1.8
1.7
0.70
0.70
V_CMOS/2 - 0.25
V_CMOS+0.3
Unit
°C
V
%
%
V
V
V
V
V
V
V
%
V
V
V
V
V
V
Table 19: Timing Conditions
Symbol
t_CYCLE
t_CR, t_CF
t_CH, t_CL
t_TR
t_DCW
t_DR, t_DF
t_S, t_H
t_DR1, t_DF1
Parameter
CTM and CFM cycle times (-600)
CTM and CFM cycle times (-711)
CTM and CFM cycle times (-800)
CTM and CFM input rise and fall times
CTM and CFM high and low times
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)^a
Domain crossing window
DQA/DQB/ROW/COL input rise/fall times
DQA/DQB/ROW/COL-to-CFM set/hold @ t_CYCLE=3.33ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t_CYCLE=2.81ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t_CYCLE=2.50ns
SIO0, SIO1 input rise and fall times
Min
Max
3.33
3.83
2.80
3.83
2.50
3.83
0.2
0.5
40%
60%
0.0
1.0
0.9
1.0
-0.1
0.1
0.2
0.65
0.275^b,d
-
0.240^c,d
-
0.200^d
-
-
5.0
Unit
ns
ns
ns
ns
t_CYCLE
t_CYCLE
t_CYCLE
ns
ns
ns
ns
ns
Figure(s)
Figure 53
Figure 53
Figure 53
Figure 53
Figure 53
Figure 42
Figure 53
Figure 59
Figure 54
Figure 54
Figure 54
Figure 54
Figure 56
Page 44
Rev. 0.9 Jan. 2000