K4R881869M Datasheet, PDF (19/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Figure 12 shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 10. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be
spaced an interval t_PACKET apart unless they are directed to
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
Different Device
Same Device
Same Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank
Adjacent Bank
Same Bank
Any Bank
Non-adjacent Bank
RR13
RR14
RR15
RR16
RR9
RR10
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
c0 = {Da,Ba+1Rc}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇ T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃ T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
PRER a0 PRER b0
t_PACKET
PRER a0
PRER c0
t_PP
PRER a0 ACT b0
t_PACKET
PRER a0 ACT c0
t_PACKET
DQA8..0
DQB8..0
Figure 12: Row Packet Examples
Row and Column Cycle Description
Activate: A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
Restore: Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write: While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
Precharge: When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
Intervals: The activate operation requires the interval
t_RCD,MIN to complete. The hidden restore operation requires
the interval t_RAS,MIN - t_RCD,MIN to complete. Column read
and write operations are also performed during the t_RAS,MIN
- t_RCD,MIN interval (if more than about four column opera-
tions are performed, this interval must be increased). The
precharge operation requires the interval t_RP,MIN to
complete.
Adjacent Banks: An RDRAM with a “s” designation
(512Kx32sx18) indicates it contains “split banks”. This
means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0, 15, 30, and
31 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.
For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 1024 bytes
loaded into each sense amp from the 2Kbyte row - 512 bytes
to the DQA side and 512 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
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Rev. 0.9 Jan. 2000