K4R881869M Datasheet, PDF (14/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
ROW-to-ROW Packet Interaction
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T
CTM/CFM
ROW2
..ROW0
ROPa a0
ROPb b0
t_RRDELAY
COL4
..COL0
DQA8..0
DQB8..0
Transaction a: ROPa a0 = {Da,Ba,Ra}
Transaction b: ROPb b0= {Db,Bb,Rb}
Figure 6: ROW-to-ROW Packet Interaction- Timing
Figure 6 shows two packets on the ROW pins separated by
an interval t_RRDELAY which depends upon the packet
contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table 10 summarizes the t_RRDELAY values
for all possible cases.
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
t_RR restriction applies to the same device with non-adjacent
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, t_RRDELAY is t_RC (t_RAS to the PRER command,
and t_RP to the next ACT).
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the t_RAS restriction means the activated bank must wait
before it can be precharged.
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba±1) is precharged or activated. In cases RR11 and
RR12, the same and adjacent banks must all wait t_RP for the
sense amp and bank to precharge before being activated.
Table 10: ROW-to-ROW Packet Interaction - Rules
Case # ROPa Da Ba Ra ROPb Db
Bb
RR1 ACT Da Ba Ra ACT /= Da xxxx
RR2 ACT Da Ba Ra ACT == Da /= {Ba,Ba+1,Ba-1}
RR3 ACT Da Ba Ra ACT == Da == {Ba+1,Ba-1}
RR4 ACT Da Ba Ra ACT == Da == {Ba}
RR5 ACT Da Ba Ra PRER /= Da xxxx
RR6 ACT Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1}
RR7 ACT Da Ba Ra PRER == Da == { Ba+1,Ba-1}
RR8 ACT Da Ba Ra PRER == Da == {Ba}
RR9 PRER Da Ba Ra ACT /= Da xxxx
RR10 PRER Da Ba Ra ACT == Da /= {Ba,Ba±1,Ba±2}
RR10a PRER Da Ba Ra ACT == Da == {Ba+2}
RR10b PRER Da Ba Ra ACT == Da == {Ba-2}
RR11 PRER Da Ba Ra ACT == Da == {Ba+1,Ba-1}
RR12 PRER Da Ba Ra ACT == Da == {Ba}
RR13 PRER Da Ba Ra PRER /= Da xxxx
RR14 PRER Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1}
RR15 PRER Da Ba Ra PRER == Da == {Ba+1,Ba-1}
RR16 PRER Da Ba Ra PRER == Da == Ba
Rb t_RRDELAY
x..x t_PACKET
x..x t_RR
x..x t_RC - illegal unless PRER to Ba/Ba+1/Ba-1
x..x t_RC - illegal unless PRER to Ba/Ba+1/Ba-1
x..x t_PACKET
x..x t_PACKET
x..x t_RAS
x..x t_RAS
x..x t_PACKET
x..x t_PACKET
x..x t_PACKET/t_RP if Ba+1 is precharged/activated.
x..x t_PACKET/t_RP if Ba-1 is precharged/activated.
x..x t_RP
x..x t_RP
x..x t_PACKET
x..x t_PP
x..x t_PP
x..x t_PP
Example
Figure 11
Figure 11
Figure 10
Figure 10
Figure 11
Figure 11
Figure 10
Figure 15
Figure 12
Figure 12
Figure 10
Figure 10
Figure 12
Figure 12
Figure 12
Figure 12
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Rev. 0.9 Jan. 2000