K4R881869M Datasheet, PDF (55/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t_PROP1 parameter specified this propagation
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t_DR1 and t_DF1, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are t_QR1 and
t_QF1, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, imformation
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t_TR parameter permits
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t_DCW is needed in order to describe how
the delay between a RD command packet and read data
packet varies as a function of the t_TR value.
Figure 59 shows this timing for five distinct values of t_TR.
Case A (t_TR=0) is what has been used throughout this docu-
ment. The delay between the RD command and read data is
t_CAC. As t_TR varies from zero to t_CYCLE (cases A through
E), the command to data delay is (t_CAC-t_TR). When the t_TR
value is in the range 0 to t_DCW,MAX, the command to data
delay can also be (t_CAC-t_TR-t_CYCLE). This is shown as cases
A’and B’(the gray packets). Similarly, when the t _TR value
is in the range (t_CYCLE+t_DCW,MIN) to t_CYCLE, the command
to data delay can also be (t_CAC-t_TR+t_CYCLE). This is shown
as cases D’ and E’ (the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
CFM
COL
RD a1
t_CYCLE
CTM
DQA/B
t_TR
DQA/B
Case A t_TR=0
Case A’ t_TR=0
t_CAC-t_TR
t_CAC -t_TR-t_CYCLE
Q(a1)
Q(a1)
CTM
DQA/B _tTR
DQA/B
Case B t_TR=t_DCW,MAX
Case B’ t_TR=t_DCW,MAX
t_CAC-t_TR
t_CAC-t_TR-t_CYCLE
Q(a1)
Q(a1)
CTM
DQA/B
t_{TR Case C tTR=0.5•t CYCLE}
t_CAC-t_TR
Q(a1)
CTM
DQA/B
t_TR
Case D t_TR=t_CYCLE+t_DCW,MIN
DQA/B
Case D’ t_TR=t_CYCLE+t_DCW,MIN
t_CAC-t_TR
t_CAC-t_TR+t_CYCLE
Q(a1)
Q(a1)
CTM
DQA/B t_TR
DQA/B
Case E t_TR=t_CYCLE
Case E’ t_TR=t_CYCLE
t_CAC-t_TR
t_CAC-t_TR+t_CYCLE
Figure 59: RSL Transmit - Crossing Read Domains
Q(a1)
Q(a1)
Page 53
Rev. 0.9 Jan. 2000