K4R881869M Datasheet, PDF (43/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇ T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃ T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
SCK
If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).
t_S3 t_H3 t_S3 t_H3
t_CE
PDEV5..0^b PDEV5..0^b
DQS=0 ^b,c _{DQS=1 b}
No ROW packets may
overlap the restricted interval
No COL packets may
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states
ROP
restricted
ROP
COP
XOP
t_S4 t_H4
restricted
t_S4 t_H4
COP
XOP
CMD
SIO0
SIO1
01
0/1^a
The packet is repeated
from SIO0 to SIO1
0/1^a
Effective hold becomes
t_H4’=t _H4+[PDNXA•64•t _SCYCLE+t_PDNXB,MAX]-[PDNX•256•t _SCYCLE]
if [PDNX•256•t _SCYCLE] < [PDNXA•64•t _SCYCLE+t_PDNXB,MAX].
(NAPX)•t _SCYCLE)/(256•PDNX•t _SCYCLE)
Power
State
NAP/PDN
DQS=0 ^b DQS=1^b
a _{Use 0 for NAP exit, 1 for PDN exit}
b _{Device selection timing slot is selected by DQS field of NAPX register}
STBY/ATTN^d
c _{The DQS field must be written with “1“ for this RDRAM.}
d _{Exit to STBY or ATTN depends upon whether RLXR was}
asserted at NAP or PDN entry time
Figure 48: NAP and PDN Exit
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁
CTM/CFM
CTM/CFM
ROW2
..ROW0
NAP entry
NAPR
ROW2
..ROW0
PDN entry
PDNR
SCK
SCK
NAP exit
CMD
01
t_NU0
no entry to NAP or PDN
t_NU0 = 5•t _CYCLE + (2+NAPX)•t _SCYCLE
t_NU1 = 8•t _CYCLE - (0.5•t _SCYCLE)
if NSR=0
= 23•t _CYCLE
if NSR=1
t_NU1
no exit
0 1 CMD
PDN exit
01
01
t_PU0
no entry to NAP or PDN
t_PU1
no exit
t_PU0 = 5•t _CYCLE + (2+256•PDNX)•t _SCYCLE
t_PU1 = 8•t _CYCLE - (0.5•t _SCYCLE)
if PSR=0
= 23•t _CYCLE
if PSR=1
Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
Page 41
Rev. 0.9 Jan. 2000