K4R881869M Datasheet, PDF (52/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
CMOS - Receive Timing
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals .
The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller (or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The cycle time, high phase time, and low phase time of the
SCK clock are t_CYCLE1, t_CH1 and t_CL1, all measured at the
SCK
t_DR2
50% level. The rise and fall times of SCK, CMD, and SIO0
are t_DR1 and t_DF1, measured at the 20% and 80% levels.
The CMD signal is sampled twice per t_CYCLE1 interval, on
the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t_S1/t_H1. The
SCK and CMD timing points are measured at the 50% level.
The SIO0 signal is sampled once per t_CYCLE1 interval on the
falling edge. The set/hold window of the sample points is
t_S2/t_H2. The SCK and SIO0 timing points are measured at the
50% level.
V_IH,CMOS
80%
50%
t_DF2
CMD
t_DR2
t_CYCLE1
t_CH1
t_S1
t_H1
t_CL1
t_S1
t_H1
even
odd
20%
V_IL,CMOS
V_IH,CMOS
80%
50%
t_DR1
SIO0
t_DF2
t_S2
t_H2
20%
V_IL,CMOS
V_IH,CMOS
80%
50%
t_DF1
Figure 56: CMOS Timing - Data Signals for Receive
20%
V_IL,CMOS
Page 50
Rev. 0.9 Jan. 2000