K4R881869M Datasheet, PDF (25/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Write/Retire Examples - continued
The RD will prevent a retire of the first WR from automati-
cally happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.
Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of t_PACKET. This situa-
tion is explicitly shown in Table 12 for the cases in which
t_CCDELAY is equal to t_RTR.
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
The retire operation for a write can be
held off by a read to the same device
WR a1
t_CAC
RD b1 retire (a1)
MSK (a1)
t_RTR + t_PACKET
D (a1)
t_CWD
Transaction a: WR
Transaction b: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
CTM/CFM
ROW2
..ROW0
COL4
..COL0
Q (Db1Q) A8..0
DQB8..0
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
WR a1
WR b1 retire (a1) RD c1
MSK (a1)
t_RTR
D (a1) D (b1)
t_CAC
t_CWD
Transaction a: WR
Transaction b: WR
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
c1= {Da,Bc,Cc1}
Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automati-
cally performed, it is made to this new row, since the write
buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn’t
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time t_RTR before or earlier.
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇ T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃ T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT a0
t_RC
PRER a2
The retire operation puts the
write data in the new row
ACT c0
WR a1
t_RCD
t_RAS
RD b1
RD b2
t_RTR
D (a1)
RD b3
t_RP
RD b4 RD b5
RD b6 retire (a1)
MSK (a1)
Q (b1) Q (b2) Q (b3) Q (b4) Q (b5)
Transaction a: WR
Transaction b: RD
Transaction c: WR
t_CWD
t_CAC
a0 = {Da,Ba,Ra}
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
c0 = {Da,Ba,Rc}
a1 = {Da,Ba,Ca1}
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a2 = {Da,Ba}
b3= {Da,Bb,Cb3}
b6 = {Da,Bb,Cb6}
WARNING
This sequence is hazardous
and must be used with caution
Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
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Rev. 0.9 Jan. 2000