K4R881869M Datasheet, PDF (47/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
Table 19: Timing Conditions
Symbol
t_DR2, t_DF2
t_CYCLE1
t_CH1, t_CL1
t_S1
t_H1
t_S2
t_H2
t_S3
t_H3
t_S4
t_H4
v_IL,CMOS
v_IH,CMOS
t_NPQ
t_READTOCC
t_CCSAMTOREAD
t_CE
t_CD
t_FRM
t_NLIMIT
t_REF
t_CCTRL
t_TEMP
t_TCEN
t_TCAL
t_TCQUIET
t_PAUSE
Parameter
Min
Max
CMD, SCK input rise and fall times
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions
SCK high and low times
CMD setup time to SCK rising or falling edge^e
CMD hold time to SCK rising or falling edge^e
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window^f
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM delay (no RSL operations allowed)
-
1000
10
4.25
1.25
1
40
40
0
5.5
-1
5
- 0.7
V_CMOS/2
+ 0.4
4
12
8
2
100
7
34 t_CYCLE
150
2
140
2.0
-
-
-
-
-
-
-
-
-
-
-
V_CMOS/2 -
0.4
V_CMOS +
0.7
-
-
-
-
-
-
10.0
32
100ms
100
-
2
-
200.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CYCLE
t_CYCLE
V
V
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
µs
ms
ms/t_CYCLE
ms
t_CYCLE
t_CYCLE
t_CYCLE
µs
Figure(s)
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 48,
Figure 57
Figure 48
Figure 48
Figure 47
Figure 51
Figure 51
Figure 48
Figure 47
Figure 46
Figure 45
Figure 50
Figure 51
Figure 52
Figure 52
Figure 52
Figure 52
page 28
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t_CYCLE=3.33ns.
c. This parameter also applies to a -800 part when operated with t_CYCLE=2.81ns.
d. t_S,MIN and t_H,MIN for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLE values.
e. With V_IL,CMOS=0.5V_CMOS-0.4V and V_IH,CMOS=0.5V_CMOS+0.4V
f. Effective hold becomes t_H4’=t _H4+[PDNXA•64•t _SCYCLE+t_PDNXB,MAX]-[PDNX•256•t _SCYCLE]
if [PDNX•256•t _SCYCLE] < [PDNXA•64•t _SCYCLE+t_PDNXB,MAX]. See Figure 48.
Page 45
Rev. 0.9 Jan. 2000