K4R881869M Datasheet, PDF (49/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
RSL - Clocking
Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
Most timing is measured relative to the points where they
cross. The t_CYCLE parameter is measured from the falling
CTM edge to the falling CTM edge. The t_CL and t_CH param-
eters are measured from falling to rising and rising to falling
edges of CTM. The t_CR and t_CF rise- and fall-time parame-
ters are measured at the 20% and 80% points.
CTM
t_CYCLE
t_CL
V_X-
t_CH
t_CR
t_CR
V_CM
V_X+
V_CIH
80%
50%
CTMN
t_TR
CFM
V_X-
t_CF
t_CR
t_CF
t_CR
V_CM
V_X+
20%
V_CIL
V_CIH
80%
50%
CFMN
t_CL
t_CYCLE
t_CF
t_CH
20%
V_CIL
t_CF
Figure 53: RSL Timing - Clock Signals
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The t_CYCLE parameter is measured from
the falling CFM edge to the falling CFM edge. The t_CL and
t_CH parameters are measured from falling to rising and rising
to falling edges of CFM. The t_CR and t_CF rise- and fall-time
parameters are measured at the 20% and 80% points.
The t_TR parameter specifies the phase difference that may be
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
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Rev. 0.9 Jan. 2000