K4R881869M Datasheet, PDF (28/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
allow an application to select the appropriate operating mode
of the RDRAM.
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
SCK ^T4
T₂₀
CMD
1111 0000
SIO0
SIO1
00000000...00000000
00000000...00000000
SRQ - SWR command
SA
Each packet is repeated
from SIO0 to SIO1
SRQ - SWR command
SA
T₃₆
00000000...00000000
SD
SD
T₅₂
T₆₈
1
0
next transaction
1
00000000...00000000
1111
0
1
SINT
0
1
SINT
0
Figure 23: Serial Write (SWR) Transaction to Control Register
Write and read transactions are each composed of four
packets, as shown in Figure 23 and Figure 24. Each packet
consists of 16 bits, as summarized in Table 14 and Table 15.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the trans-
action type. The SDEV5..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)
packet contains a 12 bit address for selecting a control
register.
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.
SCK ^T4
T₂₀
T₃₆
T₅₂
T₆₈
1
CMD
1111 0000
SIO0
SIO1
00000000...00000000
00000000...00000000
SRQ - SRD command
SA
First 3 packets are repeated
from SIO0 to SIO1
SRQ - SRD command
SA
00000000...00000000
addressed RDRAM drives
0/SD15..SD0/0 on SIO0
SINT
SINT
0
next transaction
1
00000000...00000000
controller drives
0 on SIO0
1111
0
1
0
SD
0
0
non-addressed RDRAMs pass
0/SD15..SD0/0 from SIO1 to SIO0
1
0
SD
0
0
Figure 24: Serial Read (SRD) Transaction Control Register
Page 26
Rev. 0.9 Jan. 2000