K4R881869M Datasheet, PDF (41/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
able to frame COL packets (TFRM is a control register field
- see Figure 40). Once in ATTN state, the RDRAM will
automatically transition to the ATTNW and ATTNR states
as it receives WR and RD commands.
ATTNR
automatic
automatic
ATTNW
ATTN
NAPR • RLXR
PDEV.CMD•SIO0
NAPR • RLXR
PDEV.CMD•SIO0
t_NLIMIT
NAP-A
NAP
NAP-S
PDNR • RLXR
PDEV.CMD•SI O0
PDNR • RLXR
PDEV.CMD•SI O0
PDN-A
PDN
PDN-S
STBY
SETR/CLRR
Notation:
SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets
PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)•(CMD=01)
ATTN - ROWA packet (non-broadcast) or ROWR packet
(non-broadcast) with ATTN command
Figure 45: Power State Transition Diagram
Once the RDRAM is in ATTN, ATTNW, or ATTNR states,
it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given
in an ROWR, COLC , or COLX packet (see the left side of
Figure 46). It is usually given after all banks of the RDRAM
have been precharged; if other banks are still activated, then
the RLX command would probably not be given.
If a broadcast ROWA packet or ROWR packet (with the
ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR
command is received, the RDRAM goes to STBY.
Figure 47 shows the NAP entry sequence (left). NAP state is
entered by sending a NAPR command in a ROW packet. A
time t_ASN is required to enter NAP state (this specification is
provided for power calculation purposes). The clock on
CTM/CFM must remain stable for a time t_CD after the
NAPR command.
The RDRAM may be in ATTN or STBY state when the
NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY
state when NAP is exited.
Figure 47 also shows the PDN entry sequence (right). PDN
state is entered by sending a PDNR command in a ROW
packet. A time t_ASP is required to enter PDN state (this spec-
ification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time t_CD after
the PDNR command.
The RDRAM may be in ATTN or STBY state when the
PDNR command is issued. When PDN state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with PDNR, then the RDRAM will return to STBY
state when PDN is exited. The current- and slew-rate-control
levels are re-established.
The RDRAM’s write buffer must be retired with the appro-
priate COP command before NAP or PDN are entered. Also,
all the RDRAM’s banks must be precharged before NAP or
PDN are entered. The exception to this is if NAP is entered
with the NSR bit of the INIT register cleared (disabling self-
refresh in NAP). The commands for relaxing, retiring, and
precharging may be given to the RDRAM as late as the
ROPa0, COPa0, and XOPa0 packets in Figure 47. No broad-
cast packets nor packets directed to the RDRAM entering
Nap or PDN may overlay the quiet window. This window
extends for a time t_NPQ after the packet with the NAPR or
PDNR command.
Figure 48 shows the NAP and PDN exit sequences. These
sequences are virtually identical; the minor differences will
be highlighted in the following description.
Before NAP or PDN exit, the CTM/CFM clock must be
stable for a time t_CE. Then, on a falling and rising edge of
SCK, if there is a “01” on the CMD input, NAP or PDN state
will be exited. Also, on the falling SCK edge the SIO0 input
must be at a 0 for NAP exit and 1 for PDN exit.
If the PSX bit of the INIT register is 0, then a device
PDEV5..0 is specified for NAP or PDN exit on the DQA5..0
pins. This value is driven on the rising SCK edge 0.5 or 1.5
SCK cycles after the original falling edge, depending upon
the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the
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Rev. 0.9 Jan. 2000