K4R881869M Datasheet, PDF (50/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per t_CYCLE interval.
The set/hold window of the sample points is t_S/t_H. The
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V_REF voltage point of the input transition.
The t_DR and t_DF rise- and fall-time parameters are measured
at the 20% and 80% points of the input transition.
CFM
CFMN
DQA
DQB
ROW
COL
V_X-
t_DR
V_CM
V_X+
0.5•t _CYCLE
t_S
t_H
t_S
t_H
even
odd
t_DF
Figure 54: RSL Timing - Data Signals for Receive
V_CIH
80%
50%
20%
V_CIL
V_DIH
80%
V_REF
20%
V_DIL
Page 48
Rev. 0.9 Jan. 2000