K4R881869M Datasheet, PDF (31/64 Pages) Samsung semiconductor – 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R881869M
Preliminary
Direct RDRAM^™
between a ROW packet with an activate command and
the COL packet with a read or write command.
o 3.12 SETR/CLRR - Each RDRAM is given a SETR
command and a CLRR command through the SIO
block. This sequence performs a second reset operation
on the RDRAMs.
o 3.13 Write CCA and CCB Registers - These registers
are written with a value halfway between their
minimum and maximum values. This shortens the time
needed for the RDRAMs to reach their steady-state
current control values in stage 5.0.
o 3.14 Powerdown Exit - The RDRAMs are in the PDN
power state at this point. A broadcast PDNExit
command is performed by the SIO block to place the
RDRAMs in the RLX (relax) power state in which they
are ready to receive ROW packets.
o 3.15 SETF - Each RDRAM is given a SETF command
through the SIO block. One of the operations performed
by this step is to generate a value for the AS (autoskip)
bit in the SKIP register and fix the RDRAM to a partic-
ular read domain.
4.0 Controller Configuration- This stage initializes the
controller block. Each step of this stage will set a field of the
ConfigRMC[63:0] bus to the appropriate value. Other
controller implementations will have similar initialization
requirements, and this stage may be used as a guide.
o 4.1 Initial Read Data Offset- The ConfigRMC bus is
written with a value which determines the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
value written sets RMC.d1 to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.
o 4.2 Configure Row/Column Timing - This step deter-
mines the values of the t_RAS,MIN, t_RP,MIN, t_RC,MIN,
t_RCD,MIN, t_RR,MIN, and t_PP,MIN RDRAM timing param-
eters that are present in the system. The ConfigRMC
busis written with values that will be compatible with
all RDRAM devices that are present.
o 4.3 Set Refresh Interval - This step determines the
values of the t_REF,MAX RDRAM timing parameter that
are present in the system. The ConfigRMC bus is
written with a value that will be compatible with all
RDRAM devices that are present.
o 4.4 Set Current Control Interval - This step deter-
mines the values of the t_CCTRL,MAX RDRAM timing
parameter that are present in the system. The Confi-
gRMC bus is written with a value that will be compat-
ible with all RDRAM devices that are present.
o 4.5 Set Slew Rate Control Interval - This step deter-
mines the values of the t_TEMP,MAX RDRAM timing
parameter that are present in the system. The Confi-
gRMC bus is written with a value that will be compat-
ible with all RDRAM devices that are present.
o 4.6 Set Bank/Row/Col Address Bits - This step deter-
mines the number of RDRAM bank, row, and column
address bits that are present in the system. It also deter-
mines the RDRAM core types (independent, doubled,
or split) that are present. The ConfigRMC bus is written
with a value that will be compatible with all RDRAM
devices that are present.
5.0 RDRAM Current Control - This step causes the INIT
block to generate a sequence of pulses which performs
RDRAM maintainance operations.
6.0 RDRAM Core, Read Domain Initialization- This
stage completes the RDRAM initialization
o 6.1 RDRAM Core Initialization - A sequence of 192
memory refresh transactions is performed in order to
place the cores of all RDRAMs into the proper oper-
ating state.
o 6.2 RDRAM Read Domain Initialization - A memory
write and memory read transaction is performed to each
RDRAM to determine which read domain each
RDRAM occupies. The programmed delay of each
RDRAM is then adjusted so the total RDRAM read
delay (propagation delay plus programmed delay) is
constant. The TPARM and TCDLY1 registers of each
RDRAM are rewritten with the appropriate read delay
values. The ConfigRMC bus is also rewritten with an
updated value.
7.0 Other RDRAM Register Fields - This stage rewrites
the INIT register with the final values of the LSR, NSR, and
PSR fields.
In essence, the controller must read all the read-only config-
uration registers of all RDRAMs (or it must read the SPD
device present on each RIMM), it must process this informa-
tion, and then it must write all the read-write registers to
place the RDRAMs into the proper operating mode.
Initialization Note [1]: During the initialization process, it is
necessary for the controller to perform 128 current control
operations (3xCAL, 1xCAL/SAM) and one temperature
calibrate operation (TCEN/TCAL) after reset or after power-
down (PDN) exit.
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Rev. 0.9 Jan. 2000