RX24U Datasheet, PDF (98/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.26 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
Simple
SPI
(SCI1,
SCI5,
SCI6,
SCI8,
SCI9)
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
t_SPcyc
4
65536
t_Pcyc Figure 5.45
6
—
t_Pcyc
t_SPCKWH
0.4
0.6
t_SPcyc
t_SPCKWL
0.4
0.6
t_SPcyc
t_SPCKr, t_SPCKf
—
20
ns
Data input setup time (master)
VCC = 4.0 V or
t_SU
above
40
—
ns
Figure 5.46,
Figure 5.47
VCC = 2.7 V or
above
65
—
Data input setup time (slave)
40
—
Data input hold time
SS input setup time
SS input hold time
Data output delay time (master)
Data output delay time (slave)
VCC = 4.0 V or
above
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
3
—
t_SPcyc
3
—
t_SPcyc
—
40
ns
—
40
VCC = 2.7 V or
above
—
65
Data output hold time
Master
Slave
t_OH
–10
—
ns
–10
—
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
t_Dr, t_Df
—
20
ns
t_SSLr, t_SSLf
—
20
ns
t_SA
—
6
t_Pcyc Figure 5.48,
t_REL
—
6
t_Pcyc
Figure 5.49
Note 1. t_Pcyc: PCLK cycle
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 98 of 131