RX24U Datasheet, PDF (5/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
1. Overview
Table 1.1
Outline of Specifications (4/4)
Classification Module/Function
Description
12-bit A/D converter (S12ADF)
• 12 bits (5 channels × 2 units/12 channels × 1 unit)
• 12-bit resolution
• Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 40 MHz
• Operating modes
Scan mode (single scan mode, continuous scan mode, and 3 group scan mode)
Group A priority control (only for 3 group scan mode)
• Sampling variable
Sampling time can be set up for each channel
• Self-diagnostic function
• Double trigger mode (A/D conversion data duplicated)
• Assist on analog input disconnection detection
• A/D conversion start conditions
A software trigger, a trigger from a timer (MTU3, GPT, TMR), or an external trigger signal
• Sample-and-hold function
Sample-and-hold circuit included (3 channels for unit 1)
• Amplification of input signals by a programmable gain amplifier (1 channel for unit 0, 3 channels for
unit 1)
Amplification rate: 2.0 times, 2.5 times, 3.077 times, 3.636 times, 4.0 times, 4.444 times, 5.0 times,
6.667 times, 8.0 times, 10.0 times, 13.333 times (total of 11 steps)
Comparator C (CMPC)
• 4 channels
• Function to compare the reference voltage and the analog input voltage
• Reference voltage: DA0 or DA1 output is selectable
• Analog input voltage is selectable from 4 inputs
8-bit D/A converter (DAa)
• 2 channels
• 8-bit resolution
• Output voltage: 0 V to AVCC2
Safety
Memory protection unit
(MPU)
• Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to FFFF FFFFh.
• Minimum protection unit: 16 bytes
• Reading from, writing to, and enabling the execution access can be specified for each area.
• An address exception occurs when the detected access is not in the permitted area.
Register write protection
function
CRC calculator (CRC)
• Protects important registers from being overwritten for in case a program runs out of control.
• CRC code generation for arbitrary amounts of data in 8-bit units
• Select any of three generating polynomials:
X⁸ + X² + X + 1, X¹⁶ + X¹⁵ + X² + 1, or X¹⁶ + X¹² + X⁵ + 1
• Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Main clock oscillation stop
function
• Main clock oscillation stop detection: Available
Clock frequency accuracy • Monitors the clock output from the main clock oscillator, high-speed on-chip oscillator, low-speed on-
measurement circuit (CAC)
chip oscillator, the PLL frequency synthesizer, IWDT-dedicated on-chip oscillator, and PCLKB.
Data operation circuit (DOC) The function to compare, add, or subtract 16-bit data
Power supply voltages/Operating frequencies VCC = 2.7 to 5.5 V: 80 MHz
Packages
144-pin LFQFP 0.5 mm pitch
100-pin LFQFP 0.5 mm pitch
On-chip debugging system
E1 emulator (FINE interface)
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 5 of 131