RX24U Datasheet, PDF (72/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Item
Symbol
Typ.
*⁷
Max.
Unit
Test
Conditions
Supply
current
*¹
High-speed
operating mode
Deep sleep
mode
No peripheral
operation*²
ICLK = 80 MHz
ICLK = 64 MHz
ICLK = 32 MHz
I_CC
3.4 — mA
2.9 —
2.5 —
ICLK = 16 MHz
2.3 —
ICLK = 8 MHz
2.2 —
All peripheral
ICLK = 80 MHz*³
operation: Normal _{ICLK = 64 MHz*4}
22.2 —
17.9 —
ICLK = 32 MHz*⁵
12.9 —
ICLK = 16 MHz*⁵
7.6 —
ICLK = 8 MHz*⁵
4.8 —
Increase during BGO operation*⁶
2.5 —
Middle-speed
Normal
No peripheral
operating modes operating mode operation*⁸
ICLK = 12 MHz*¹⁰
I_CC
ICLK = 8 MHz
5.3 — mA
4.5 —
ICLK = 1 MHz
2.5 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
8.7 —
6.9 —
2.7 —
All peripheral
ICLK = 12 MHz*¹⁰
operation: Max.*⁹
— 18.0
Sleep mode
No peripheral
operation*⁸
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
2.6 —
2.7 —
ICLK = 1 MHz
2.2 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
6.7 —
5.6 —
2.5 —
Deep sleep
mode
No peripheral
operation*⁸
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
1.8 —
2.1 —
ICLK = 1 MHz
2.1 —
All peripheral
operation:
Normal*⁹
ICLK = 12 MHz*¹⁰
ICLK = 8 MHz
ICLK = 1 MHz
5.7 —
4.8 —
2.3 —
Increase during BGO operation*⁶
2.5 —
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. FCLK, PCLKA, PCLKB, and
PCLKD are set to divided by 64.
Note 3. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. FCLK is set to divided by 4. PCLKA is
set to divided by 1. PCLKB and PCLKD are set to divided by 2.
Note 4. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. PCLKA is set to divided by 1. FCLK,
PCLKB, and PCLKD are set to divided by 2.
Note 5. The clock signal to peripheral modules is supplied in this state. The clock source is PLL. The frequencies of FCLK, PCLKA,
PCLKB, and PCLKD are same as ICLK.
Note 6. This is the increase when data is programmed to or erased from the ROM or E2 DataFlash during program execution.
Note 7. Values when VCC = 5 V.
Note 8. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. FCLK, PCLKA, PCLKB, and
PCLKD are set to divided by 64.
Note 9. Supply of the clock signal to peripheral modules is stopped in this state. The clock source is PLL. The frequencies of FCLK,
PCLKA, PCLKB, and PCLKD are same as ICLK.
Note 10. When the frequency of PLL is 48 MHz.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 72 of 131