RX24U Datasheet, PDF (3/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
1. Overview
Table 1.1
Outline of Specifications (2/4)
Classification
Interrupt
Module/Function
Interrupt controller (ICUb)
DMA
I/O ports
Data transfer controller
(DTCa)
General I/O ports
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 3 (MTU3d)
Port output enable 3
(POE3A)
Description
• Interrupt vectors: 175
• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
• Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
• 16 levels specifiable for the order of priority
• Transfer modes: Normal transfer, repeat transfer, and block transfer
• Activation sources: Interrupts
• Chain transfer function
144-/100-pin
• I/O: 110/79
• Input: 1/1
• Pull-up resistors: 110/79
• Open-drain outputs: 90/61
• 5-V tolerance: 2/2
Capable of selecting the input/output function from multiple pins
• 9 units (16 bits × 9 channels)
• Provides up to 28 pulse-input/output lines and three pulse-input lines
• Select from among fourteen counter-input clock signals for each channel (PCLK/1, PCLK/2, PCLK/4,
PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,
MTCLKD, MTIOC1A) other than channel 1/3/4/6/7, for which only eleven signals are available,
channel 2 for 12, channel 5 for 10
• 43 general registers including 28 output compare/input capture registers
• Counter clear operation (with compare match- or input capture-sourced simultaneous counter clear
capability)
• Simultaneous writing to multiple timer counters (TCNT)
• Simultaneous register input/output by synchronous counter operation
• Buffer operation
• Cascaded operation
• 45 interrupt sources
• Automatic transfer of register data
• Pulse output modes: Toggle/PWM/complementary PWM/reset-synchronized PWM
• Complementary PWM output mode
3-phase non-overlapping waveform output for inverter control
Automatic dead time setting
Adjustable PWM duty cycle: from 0 to 100%
A/D conversion request delaying function
Interrupt at crest/trough can be skipped
Double buffer function
• Reset-synchronized PWM mode
Outputs three phases each for positive and negative PWM waveforms in user-specified duty cycle
• Phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2)
• Dead time compensation counter function
• A/D converter start trigger can be generated
• A/D converter start triggers can be skipped
• Signals from the input capture and external counter clock pins are input via a digital filter
• High impedance control of the MTU3/GPT waveform output pins and switching them to operate as
general I/O ports
• Startup by input from signal sources on 6 pins (POE0#, POE4#, POE8#, POE10#, POE11#, and
POE12#)
• Startup by detection of short-circuited outputs (detection of simultaneous PMW output at the active
level)
• Startup on detection of oscillation stopping or by a comparator, or under software control
• Control of the addition of pins for output control is programmable
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
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