RX24U Datasheet, PDF (122/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5.11 E2 DataFlash Characteristics
5. Electrical Characteristics
Table 5.43 E2 DataFlash Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time
After 10000 times of
N_DPEC
After 100000 times of
N_DPEC
After 1000000 times of
N_DPEC
Symbol
N_DPEC
t_DDRP
Min.
100000
20*^2, *³
5*^2, *³
—
Typ.
1000000
—
Max.
—
—
—
—
1*^2, *³
—
Unit
Times
Year
Conditions
T_a = +85°C
Year
Year T_a = +25°C
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 100000), erasing can be performed n times for each block. For instance, when 1-byte programming
is performed 1000 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle
is counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
Note 3. This result is obtained from reliability testing.
Table 5.44 E2 DataFlash Characteristics (2): High-Speed Operating Mode
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V,
Temperature range for the programming/erasure operation: T_a = –40 to +85°C
FCLK = 1 MHz
FCLK = 32 MHz
Item
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Programming time
1-byte
t_Dp1
—
95.0
797.0
—
Erasure time
1-Kbyte
t_DE1K
—
19.5
498.5
—
8-Kbyte
t_DE8K
—
119.8
2555.7
—
Blank check time
1-byte
t_DBC1
—
—
55.0
—
1-Kbyte
t_DBC1K
—
—
7216.0
—
Erase operation forcible stop time
t_DSED
—
—
16.0
—
Data flash-module stop release time
t_DSTOP
5.0
—
—
5.0
40.8
375.5
μs
6.2
229.4
ms
12.9
367.2
ms
—
16.1
μs
—
495.7
μs
—
10.7
μs
—
—
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 122 of 131