RX24U Datasheet, PDF (101/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.29 Timing of On-Chip Peripheral Modules (7)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = 2.7 V to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Max.
Unit
Test
Conditions
Simple I²C
(Standard mode)
(SCI1, SCI5, SCI6,
SCI8, SCI9, SCI11)
SDA rise time
SDA fall time
SDA spike pulse removal time
Data setup time
Data hold time
SCL, SDA capacitive load
Simple I²C
(Fast mode)
(SCI, SCI5, SCI6,
SCI8, SCI9, SCI11)
SDA rise time
SDA fall time
SDA spike pulse removal time
Data setup time
Data hold time
SCL, SDA capacitive load
t_Sr
—
1000
ns Figure 5.50
t_Sf
—
300
ns
t_SP
0
4 × t_Pcyc*¹
ns
t_SDAS
250
—
ns
t_SDAH
0
—
ns
C_b*²
—
400
pF
t_Sr
—
300
ns Figure 5.50
t_Sf
—
300
ns
t_SP
0
4 × t_Pcyc*¹
ns
t_SDAS
100
—
ns
t_SDAH
0
—
ns
C_b*²
—
400
pF
Note 1. t_Pcyc: PCLKB cycle
Note 2. C_b is the total capacitance of the bus lines.
PCLK
Port
t_PRW
Figure 5.34 I/O Port Input Timing
PCLKA
Output
compare output
Input capture
input
t_TICW
Figure 5.35 MTU3 Input/Output Timing
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 101 of 131