RX24U Datasheet, PDF (97/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.25 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 =AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
RSPI RSPCK clock
cycle
Master
Slave
t_SPcyc
2
6
4096
—
t_Pcyc Figure 5.45
RSPCK clock Master VCC = 4.0 V or above
t_SPCKWH (t_SPcyc – t_SPCKr –
—
ns
high pulse width
t_SPCKf)/2 – 5
VCC = 2.7 V or above
(t_SPcyc – t_SPCKr –
—
t_SPCKf)/2 – 8
Slave
(t_SPcyc – t_SPCKr –
—
t_SPCKf)/2
RSPCK clock Master VCC = 4.0 V or above
t_SPCKWL (t_SPcyc – t_SPCKr –
—
ns
low pulse width
t_SPCKf)/2 – 5
VCC = 2.7 V or above
(t_SPcyc – t_SPCKr–
—
t_SPCKf)/2 – 8
Slave
(t_SPcyc – t_SPCKr –
—
t_SPCKf)/2
RSPCK clock
rise/fall time
Output VCC = 4.0 V or above
VCC = 2.7 V or above
t_SPCKr,
—
t_SPCKf
—
6
ns
10
Input
—
0.1
μs/V
Data input setup Master VCC = 4.0 V or above
time
VCC = 2.7 V or above
Slave
t_SU
10
26
20
—
ns Figure 5.46
—
to
Figure 5.49
—
Data input hold Master RSPCK set to a division ratio
t_H
time
other than PCLKB divided by 2
t_Pcyc
—
ns
RSPCK set to PCLKB divided
t_HF
0
—
by 2
Slave
SSL setup time Master
Slave
SSL hold time Master
Slave
Data output
delay time
Master VCC = 4.0 V or above
VCC = 2.7 V or above
t_H
0
—
t_LEAD –30 + N*² × t_SPcyc
—
6
—
t_LAG –30 + N*³ × t_SPcyc
—
6
—
t_OD
—
10
—
14
ns
t_Pcyc
ns
t_Pcyc
ns
Slave
—
65
Data output hold Master
time
Slave
t_OH
0
0
—
ns
—
Successive
transmission
delay time
Master
Slave
MOSI and MISO Output
rise/fall time
Input
t_TD
t_SPcyc + 2 × t_Pcyc 8 × t_SPcyc + 2 × ns
t_Pcyc
6 × t_Pcyc
—
t_Dr, t_Df
—
10
ns
—
1
μs
SSL rise/fall
time
Output
Input
t_SSLr,
—
t_SSLf
—
10
ns
1
μs
Slave access time
Slave output release time
t_SA
—
t_REL
—
6
t_Pcyc Figure 5.48,
5
t_Pcyc ^{Figure 5.49}
Note 1. t_Pcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 97 of 131