RX24U Datasheet, PDF (45/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (17/40)
Address
0008 A105h
0008 A106h
0008 A107h
0008 A108h
0008 A109h
0008 A10Ah
0008 A10Bh
0008 A10Ch
0008 A10Dh
0008 A10Eh
0008 A10Eh
0008 A10Fh
0008 A110h
0008 A110h
0008 A111h
0008 A112h
0008 A120h
0008 A121h
0008 A122h
0008 A123h
0008 A124h
0008 A125h
0008 A126h
0008 A127h
0008 A128h
0008 A129h
0008 A12Ah
0008 A12Bh
0008 A12Ch
0008 A12Dh
0008 A12Eh
0008 A12Eh
0008 A12Fh
0008 A130h
0008 A130h
0008 A131h
0008 A132h
0008 B000h
0008 B001h
0008 B002h
0008 B003h
0008 B004h
0008 B006h
0008 B008h
0008 B00Ah
0008 B080h
0008 B082h
0008 B084h
0008 C000h
0008 C001h
0008 C002h
0008 C003h
Module
Symbol
SCI8
SMCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SMCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
DOC
DOC
DOC
PORT0
PORT1
PORT2
PORT3
Register Name
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
I²C Mode Register 1
I²C Mode Register 2
I²C Mode Register 3
I²C Status Register
SPI Mode Register
Transmit Data Register HL
Transmit Data Register H
Transmit Data Register L
Receive Data Register HL
Receive Data Register H
Receive Data Register L
Modulation Duty Register
Serial Mode Register
Bit Rate Register
Serial Control Register
Transmit Data Register
Serial Status Register
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
I²C Mode Register 1
I²C Mode Register 2
I²C Mode Register 3
I²C Status Register
SPI Mode Register
Transmit Data Register HL
Transmit Data Register H
Transmit Data Register L
Receive Data Register HL
Receive Data Register H
Receive Data Register L
Modulation Duty Register
CAC Control Register 0
CAC Control Register 1
CAC Control Register 2
CAC Interrupt Request Enable Register
CAC Status Register
CAC Upper-Limit Value Setting Register
CAC Lower-Limit Value Setting Register
CAC Counter Buffer Register
DOC Control Register
DOC Data Input Register
DOC Data Setting Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Register
Symbol
RDR
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
SPMR
TDRHL
TDRH
TDRL
RDRHL
RDRH
RDRL
MDDR
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
SPMR
TDRHL
TDRH
TDRL
RDRHL
RDRH
RDRL
MDDR
CACR0
CACR1
CACR2
CAICR
CASTR
CAULVR
CALLVR
CACNTBR
DOCR
DODIR
DODSR
PDR
PDR
PDR
PDR
Number of
Bits
8
8
8
8
8
8
8
8
8
16
8
8
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
8
8
16
8
8
8
8
8
8
8
8
16
16
16
8
16
16
8
8
8
8
Number of Access Cycles
Access Size ICLK ≥ PCLK
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
16
4 or 5 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
16
4 or 5 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
16
4 or 5 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
16
4 or 5 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
8
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
8
2 or 3 PCLKB
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 45 of 131