RX24U Datasheet, PDF (100/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.28 Timing of On-Chip Peripheral Modules (6)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.*^1, *²
Max.
Unit
Test
Conditions
RIIC
(Standard
mode, SMBus)
RIIC
(Fast mode)
SCL cycle time
SCL high pulse width
SCL low pulse width
SCL, SDA rise time
SCL, SDA fall time
SCL, SDA spike pulse removal time
SDA bus free time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Data setup time
Data hold time
SCL, SDA capacitive load
SCL cycle time
SCL high pulse width
SCL low pulse width
SCL, SDA rise time
SCL, SDA fall time
SCL, SDA spike pulse removal time
SDA bus free time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Data setup time
Data hold time
SCL, SDA capacitive load
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
6 (12) × t_IICcyc + 1300
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
—
—
0
3 (6) × t_IICcyc + 300
t_IICcyc + 300
1000
1000
t_IICcyc + 50
0
—
6 (12) × t_IICcyc + 600
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
—
—
0
3 (6) × t_IICcyc + 300
t_IICcyc + 300
300
300
t_IICcyc + 50
0
—
—
—
—
1000
300
1 (4) × t_IICcyc
—
—
—
—
—
—
400
—
—
—
300
300
1 (4) × t_IICcyc
—
—
—
—
—
—
400
ns Figure 5.50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns Figure 5.50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Note 1. t_IICcyc: RIIC internal reference count clock (IICφ) cycle
Note 2. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bit is 1.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 100 of 131