RX24U Datasheet, PDF (91/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.18 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol Min.
Typ. Max.
Unit
Test
Conditions
Recovery time High-speed Crystal connected to Main clock oscillator t_SBYMC —
2
from software mode
main clock oscillator operating*²
standby mode*¹
Main clock oscillator t_SBYPC —
2
and PLL circuit
operating*³
3
ms Figure 5.30
3
ms
External clock input Main clock oscillator t_SBYEX —
35
50
μs
to main clock
operating*⁴
oscillator
Main clock oscillator t_SBYPE —
70
95
μs
and PLL circuit
operating*⁵
HOCO clock
operation
HOCO clock
t_SBYHO
—
40
55
μs
oscillator operation 1
*⁶
HOCO clock
oscillator operation 2
*⁷
—
75
90
μs
HOCO clock
t_SBYPH
—
110 130
μs
oscillator, PLL circuit
operation*⁸
LOCO clock oscillator operating*⁹
t_SBYLO
—
40
55
μs
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time
when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the
system clock source. The above table applies when only the corresponding clock is operating.
When the frequency of crystal is 20 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
When the frequencies of ICLK, FCLK, PCLKA, PCLKB, and PCLKD are not divided.
When the frequency of PLL is 80 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
When the frequencies of ICLK and PCLKA are set to 80 MHz, PCLKB and PCLKD are set to 40 MHz, and FCLK is set to 20 MHz.
When the frequency of the external clock is 20 MHz.
When the frequencies of ICLK, FCLK, PCLKA, PCLKB, and PCLKD are not divided.
When the frequency of PLL is 80 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 00h.
When the frequencies of ICLK and PCLKA are set to 80 MHz, PCLKB and PCLKD are set to 40 MHz, and FCLK is set to 20 MHz.
When the frequency of the high-speed on-chip oscillator is 32 MHz. When the high-speed on-chip oscillator wait control register
(HOCOWTCR) is set to 05h. When the frequencies of ICLK, FCLK, PCLKA, PCLKB, and PCLKD are not divided.
When the frequency of the high-speed on-chip oscillator is 64 MHz. Set the high-speed on-chip oscillator wait control register
(HOCOWTCR) is set to 06h. When the frequencies of ICLK and PCLKA are set to 64 MHz, and the frequencies of PCLKB,
PCLKD, and FCLK are set to 32 MHz.
When the frequency of the high-speed on-chip oscillator is 32 MHz, and the frequency of PLL is 80 MHz. When the high-speed
on-chip oscillator wait control register (HOCOWTCR) is set to 05h. When the frequencies of ICLK and PCLKA are set to 80
MHz, the frequencies of PCLKB and PCLKD are set to 40 MHz, and the frequency of FCLK is set to 20MHz.
When the frequencies of ICLK, FCLK, PCLKA, PCLKB, and PCLKD are not divided.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 91 of 131