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RX24U Datasheet, PDF (90/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core
RX24U Group
5.3.2
Reset Timing
5. Electrical Characteristics
Table 5.17 Reset Timing
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, Ta = –40 to +85°C
Item
Symbol Min. Typ. Max.
Unit
Test Conditions
RES# pulse width
At power-on
Other than above
Wait time after RES# cancellation (at power-on)
Wait time after RES# cancellation
(during powered-on state)
tRESWP
tRESW
tRESWT
tRESWT
3
—
—
30
—
—
— 27.5 —
— 114 —
ms
Figure 5.27
μs
Figure 5.28
ms
Figure 5.27
μs
Figure 5.28
Independent watchdog timer reset period
tRESWIW
—
1
— IWDT clock Figure 5.29
cycle
Software reset period
tRESWSW
—
1
—
Wait time after independent watchdog timer reset cancellation*1 tRESW2
—
300
—
Wait time after software reset cancellation
tRESW2
—
168
—
ICLK cycle
μs
μs
Note 1. When IWDTCR.CKS[3:0] = 0000b.
VCC
RES#
Internal reset
tRESWP
Figure 5.27 Reset Input Timing at Power-On
tRESWT
RES#
Internal reset
Figure 5.28 Reset Input Timing (1)
tRESW
tRESWT
Independent watchdog timer reset
Software reset
Internal reset
Figure 5.29 Reset Input Timing (2)
tRESWIW, tRESWSW
tRESWT2
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 90 of 131