RX24U Datasheet, PDF (116/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.38 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = 0 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Wait time after power-on
reset cancellation
At normal startup
t_POR
―
28.4
―
ms Figure 5.54
Wait time after voltage monitoring 0 reset
cancellation
t_LVD0
―
568
―
μs Figure 5.55
Wait time after voltage monitoring 1 reset
cancellation
t_LVD1
―
100
―
μs Figure 5.56
Wait time after voltage monitoring 2 reset
cancellation
t_LVD2
―
100
―
μs Figure 5.57
Response delay time
Minimum VCC down time*¹
t_det
―
―
350
μs Figure 5.53
t_VOFF
350
―
―
μs Figure 5.53, VCC = 1.0 V or
above
Power-on reset enable time
t_W(POR)
1
―
―
ms Figure 5.54, VCC = below 1.0
V
LVD operation stabilization time (after LVD is
Td_(E-A)
―
enabled)
―
300
μs Figure 5.56, Figure 5.57
Hysteresis width (LVD0, LVD1 and LVD2)
V_LVH
―
70
―
mV Vdet1_0 to 4 selected
―
60
―
Vdet0_0 to 2 selected
Vdet1_5 to 8 selected
LVD2 selected
Note:
Note 1.
These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/LVD.
VCC
V_POR
1.0 V
t_VOFF
Internal reset signal
(active-low)
Figure 5.53 Voltage Detection Reset Timing
t_det t_det t_POR
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 116 of 131