RX24U Datasheet, PDF (96/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5. Electrical Characteristics
Table 5.24 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
SCI11
Input clock cycle
Asynchronous
Clock synchronous
t_Scyc
4
— t_PAcyc Figure 5.42
6
—
Input clock frequency
Asynchronous
Clock synchronous
t_Scyc
—
10 MHz
—
6.67
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
Asynchronous
t_Scyc
16
— t_PAcyc Figure 5.43
Clock synchronous
4
—
Output clock frequency
Asynchronous
Clock synchronous
t_Scyc
—
5 MHz
—
10
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time Clock synchronous
(master)
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
t_TXD
—
40 ns
Transmit data delay time Clock
VCC = 4.0 V or above
(slave)
synchronous _{VCC = 2.7 V or above}
—
40 ns
—
65 ns
Receive data setup time Clock
VCC = 4.0 V or above
(master)
synchronous _{VCC = 2.7 V or above}
t_RXS
40
— ns
65
— ns
Receive data setup time Clock synchronous
(slave)
40
— ns
Receive data hold time Clock synchronous
t_RXH
40
— ns
Note 1. t_Pcyc: PCLK cycle, t_PAcyc: PCLKA cycle
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 96 of 131