RX24U Datasheet, PDF (24/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
2. CPU
(9) Floating-point status word (FPSW)
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
2.3 Accumulator
The accumulator (ACC0 or ACC1) is a 72-bit register used for DSP instructions. The accumulator is handled as a 96-bit
register for reading and writing. At this time, when bits 95 to 72 of the accumulator are read, the value where the value of
bit 71 is sign extended is read. Writing to bits 95 to 72 of the accumulator is ignored. ACC0 is also used for the multiply
and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in
ACC0 is modified by execution of the instruction.
Use the MVTACGU, MVTACHI, and MVTACLO instructions for writing to the accumulator. The MVTACGU,
MVTACHI, and MVTACLO instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the
lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions for reading data from the accumulator. The
MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions read data from the guard bits (bits 95 to 64), higher-
order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
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