RX24U Datasheet, PDF (59/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (31/40)
Address
000A 8638h
000A 863Ah
000A 863Ah
000A 863Ch
000A 863Ch
000A 863Eh
000A 863Eh
000A 8640h
to
000A 867Eh
000A 8680h
000C 1200h
000C 1201h
000C 1202h
000C 1203h
000C 1204h
000C 1205h
000C 1206h
000C 1207h
000C 1208h
000C 1209h
000C 120Ah
000C 120Dh
000C 120Eh
000C 120Fh
000C 1210h
000C 1212h
000C 1214h
000C 1216h
000C 1218h
000C 121Ah
000C 121Ch
000C 121Eh
000C 1220h
000C 1222h
000C 1224h
000C 1226h
000C 1228h
000C 122Ah
000C 122Ch
000C 122Dh
000C 1230h
000C 1231h
000C 1232h
000C 1234h
000C 1236h
000C 1238h
000C 1239h
000C 123Ah
000C 123Bh
000C 123Ch
000C 1240h
000C 1244h
Module
Symbol
RSCAN
RSCAN0
RSCAN
RSCAN0
RSCAN
RSCAN0
RSCAN
RSCAN
RSCAN0
MTU3
MTU4
MTU3
MTU4
MTU3
MTU3
MTU4
MTU4
MTU3
MTU4
MTU
MTU
MTU
MTU
MTU3
MTU4
MTU
MTU
MTU3
MTU3
MTU4
MTU4
MTU
MTU
MTU3
MTU3
MTU4
MTU4
MTU3
MTU4
MTU
MTU
MTU
MTU
MTU
MTU3
MTU4
MTU
MTU
MTU
MTU4
MTU4
Register Name
RAM Test Register 92
Transmit Buffer Register 3CH
RAM Test Register 93
Transmit Buffer Register 3DL
RAM Test Register 94
Transmit Buffer Register 3DH
RAM Test Register 95
RAM Test Register 96 to 127
Transmit History Buffer Access Register
Timer Control Register
Timer Control Register
Timer Mode Register 1
Timer Mode Register 1
Timer I/O Control Register H
Timer I/O Control Register L
Timer I/O Control Register H
Timer I/O Control Register L
Timer Interrupt Enable Register
Timer Interrupt Enable Register
Timer Output Master Enable Register A
Timer Gate Control Register
Timer Output Control Register 1A
Timer Output Control Register 2A
Timer Counter
Timer Counter
Timer Period Data Register A
Timer Dead Time Data Register A
Timer General Register A
Timer General Register B
Timer General Register A
Timer General Register B
Timer Subcounters A
Timer Period Buffer Register A
Timer General Register C
Timer General Register D
Timer General Register C
Timer General Register D
Timer Status Register
Timer Status Register
Timer Interrupt Skipping Set Register 1A
Timer Interrupt Skipping Counters 1A
Timer Buffer Transfer Set Register A
Timer Dead Time Enable Register A
Timer Output Level Buffer Register A
Timer Buffer Operation Transfer Mode Register
Timer Buffer Operation Transfer Mode Register
Timer Interrupt Skipping Mode Register A
Timer Interrupt Skipping Set Register 2A
Timer Interrupt Skipping Counters 2A
Timer A/D Converter Start Request Control Register
Timer A/D Converter Start Request Cycle Set Register A
Register
Symbol
RPGACC92
TMDF13
RPGACC93
TMDF23
RPGACC94
TMDF33
RPGACC95
RPGACC96 to
127
Number of
Bits
16
16
16
16
16
16
16
16
THLACC0
16
TCR
8
TCR
8
TMDR1
8
TMDR1
8
TIORH
8
TIORL
8
TIORH
8
TIORL
8
TIER
8
TIER
8
TOERA
8
TGCRA
8
TOCR1A
8
TOCR2A
8
TCNT
16
TCNT
16
TCDRA
16
TDDRA
16
TGRA
16
TGRB
16
TGRA
16
TGRB
16
TCNTSA
16
TCBRA
16
TGRC
16
TGRD
16
TGRC
16
TGRD
16
TSR
8
TSR
8
TITCR1A
8
TITCNT1A
8
TBTERA
8
TDERA
8
TOLBRA
8
TBTM
8
TBTM
8
TITMRA
8
TITCR2A
8
TITCNT2A
8
TADCR
16
TADCORA
16
Number of Access Cycles
Access Size ICLK ≥ PCLK
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
2 or 3 PCLKB
16
8, 16, 32
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16
8
8
8
8, 16
8
16, 32
16
16, 32
16
16, 32
16
16, 32
16
16, 32
16
16, 32
16
16, 32
16
8, 16
8
8, 16
8
8
8
8
8, 16
8
8
8
8
16
16, 32
2 or 3 PCLKB
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
4 or 5 PCLKA
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 59 of 131