RX24U Datasheet, PDF (94/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5.3.4
Control Signal Timing
5. Electrical Characteristics
Table 5.22 Control Signal Timing
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Typ. Max. Unit
Test Conditions
NMI pulse width t_NMIW
IRQ pulse width t_IRQW
200
t_Pcyc × 2*¹
200
t_NMICK × 3.5*²
200
t_Pcyc × 2*¹
200
t_IRQCK × 3.5*³
—
—
ns NMI digital filter disabled
—
—
(NMIFLTE.NFLTEN = 0)
—
—
—
—
NMI digital filter enabled
(NMIFLTE.NFLTEN = 1)
—
—
ns IRQ digital filter disabled
—
—
(IRQFLTE0.FLTENi = 0)
—
—
—
—
IRQ digital filter enabled
(IRQFLTE0.FLTENi = 1)
t_Pcyc × 2 ≤ 200 ns
t_Pcyc × 2 > 200 ns
t_NMICK × 3 ≤ 200 ns
t_NMICK × 3 > 200 ns
t_Pcyc × 2 ≤ 200 ns
t_Pcyc × 2 > 200 ns
t_IRQCK × 3 ≤ 200 ns
t_IRQCK × 3 > 200 ns
Note:
Note 1.
Note 2.
Note 3.
200 ns minimum in software standby mode.
t_Pcyc indicates the cycle of PCLKB.
t_NMICK indicates the cycle of the NMI digital filter sampling clock.
t_IRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
t_NMIW
Figure 5.32 NMI Interrupt Input Timing
IRQ
t_IRQW
Figure 5.33 IRQ Interrupt Input Timing
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 94 of 131