RX24U Datasheet, PDF (119/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5.9 Oscillation Stop Detection Timing
5. Electrical Characteristics
Table 5.39 Oscillation Stop Detection Timing
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 =AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Detection time
t_dr
—
—
1
ms Figure 5.58
Main clock
OSTDSR.OSTDF
Low-speed clock
ICLK
t_dr
When the main clock is selected
Figure 5.58 Oscillation Stop Detection Timing
Main clock
OSTDSR.OSTDF
PLL clock
ICLK
t_dr
When the PLL clock is selected
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 119 of 131