RX24U Datasheet, PDF (120/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5.10 ROM (Flash Memory for Code Storage) Characteristics
5. Electrical Characteristics
Table 5.40 ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time
After 1000 times of N_PEC
Symbol
N_PEC
t_DRP
Min.
1000
20*^2, *³
Typ.
Max.
Unit
Conditions
—
—
Times
—
—
Year T_a = +85°C
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
Note 3. This result is obtained from reliability testing.
Table 5.41 ROM (Flash Memory for Code Storage) Characteristics (2): High-Speed Operating Mode
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V
Temperature range for the programming/erasure operation: T_a = –40 to +85°C
FCLK = 1 MHz
FCLK = 32 MHz
Item
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Programming time
8-byte
t_P8
—
112.0
967.0
—
Erasure time
2-Kbyte
t_E2K
—
8.7
278.1
—
512-Kbyte
t_E512K
—
927.8 19218.0
—
(when block
erase
command
used)
52.3
5.5
72.0
490.5
μs
214.6
ms
1678.9 ms
512-Kbyte
t_EA512K
—
(when all-
block erase
command
used)
922.7 19013.4
—
66.7
1469.2 ms
Blank check time
8-byte
2-Kbyte
Erase operation forcible stop time
Start-up area switching setting time
Access window time
ROM mode transition wait time 1
ROM mode transition wait time 2
t_BC8
—
t_BC2K
—
t_SED
—
t_SAS
—
t_AWS
—
t_DIS
2.0
t_MS
5.0
—
55.0
—
—
1840.0
—
—
18.0
—
12.3
566.5
—
12.3
566.5
—
—
—
2.0
—
—
5.0
—
16.1
μs
—
135.7
μs
—
10.7
μs
6.2
433.5
ms
6.2
433.5
ms
—
—
μs
—
—
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%.
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 120 of 131