RX24U Datasheet, PDF (8/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
MTU3d
× 9 channels
GPTB
× 4 channels
ICUb
DTCa
RX CPU
MPU
Clock
generation
circuit
MTU3d: Multi-function timer pulse unit 3
GPTB: General PWM timer
ICUb: Interrupt controller
DTCa: Data transfer controller
IWDTa: Independent watchdog timer
CRC: CRC (cyclic redundancy check) calculator
SCIg: Serial communications interface
RSPIb: Serial peripheral interface
Figure 1.2
Block Diagram
E2 DataFlash
IWDTa
CRC
SCIg × 6 channels
RSPIb × 1 channel
RIICa × 1 channel
RSCAN × 1 channel
POE3A
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
TMR × 2 channels (unit 2)
TMR × 2 channels (unit 3)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
12-bit A/D converter × 5 channels
(unit 0)
Programmable gain amplifier
× 1 channel
12-bit A/D converter × 5 channels
(unit 1)
Programmable gain amplifier
× 3 channels
Sample and hold circuit
× 3 channels
12-bit A/D converter × 12 channels
(unit 2)
Comparator C × 4 channels
8-bit D/A converter × 2 channels
DOC
CAC
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
RIICa: I²C bus interface
RSCAN: CAN module
POE3A: Port output enable 3
TMR: 8-bit timer
CMT: Compare match timer
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
MPU: Memory protection unit
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 8 of 131