RX24U Datasheet, PDF (95/131 Pages) Renesas Technology Corp – 32-bit RXv2 CPU core

RX24U Group
5.3.5
Timing of On-Chip Peripheral Modules
5. Electrical Characteristics
Table 5.23 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = AVCC1 = AVCC2 = VREFH0 = VREFH1 = VREFH2 = VCC to 5.5 V,
VSS = AVSS0 = AVSS1 = AVSS2 = VREFL0 = VREFL1 = VREFL2 = 0 V, T_a = –40 to +85°C
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
I/O ports
MTU3
Input data pulse width
Input capture input pulse width
Single-edge setting
Both-edge setting
t_PRW
t_TICW
1.5
— t_Pcyc Figure 5.34
1.5
— t_PAcyc Figure 5.35
2.5
—
Timer clock pulse width
Single-edge setting
t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
— t_PAcyc Figure 5.36
—
Phase counting mode
2.5
—
POE3
GPT
POE# input pulse width
Input capture input pulse width
t_POEW
1.5
— t_Pcyc Figure 5.37
Single-edge setting
t_GTICW
1.5
— t_PAcyc Figure 5.38
Both-edge setting
2.5
—
External trigger input pulse width
Single-edge setting
t_GTETW
1.5
— t_PAcyc Figure 5.39
Both-edge setting
2.5
—
TMR
Timer clock pulse width
Timer clock pulse width
t_GTCKWH
1.5
t_GTCKWL
Single-edge setting
t_TMCWH,
1.5
Both-edge setting
t_TMCWL
2.5
— t_PAcyc Figure 5.40
— t_Pcyc Figure 5.41
—
SCI1, SCI5,
SCI6, SCI8,
SCI9
Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
Asynchronous
Clock synchronous
Asynchronous
Clock synchronous
t_Scyc
t_SCKW
t_SCKr
t_SCKf
t_Scyc
4
— t_Pcyc Figure 5.42
6
—
0.4
0.6 t_Scyc
—
20 ns
—
20 ns
16
— t_Pcyc Figure 5.43
4
—
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time Clock synchronous
(master)
t_SCKW
t_SCKr
t_SCKf
t_TXD
0.4
0.6 t_Scyc
—
20 ns
—
20 ns
—
40 ns
Transmit data delay time Clock
VCC = 4.0 V or above
(slave)
synchronous _{VCC = 2.7 V or above}
—
40 ns
—
65 ns
Receive data setup time Clock
VCC = 4.0 V or above
t_RXS
(master)
synchronous _{VCC = 2.7 V or above}
40
— ns
65
— ns
Receive data setup time Clock synchronous
(slave)
40
— ns
Receive data hold time Clock synchronous
A/D converter Trigger input pulse width
CAC
CACREF input pulse width
t_Pcyc ≤ t_cac*2
t_Pcyc > t_cac*2
t_RXH
40
— ns
t_TRGW
1.5
— t_Pcyc Figure 5.44
t_CACREF 4.5 t_cac + 3 t_Pcyc —
ns
5 t_cac + 6.5 t_Pcyc
Note 1. t_Pcyc: PCLK cycle, t_PAcyc: PCLKA cycle
Note 2. t_cac: CAC count clock source cycle
R01DS0278EJ0100 Rev.1.00
Mar 31, 2017
Page 95 of 131