RX634 Datasheet, PDF (96/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
5.6 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.34 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Item
Symbol
Min.
Typ.
Max. Unit Test Conditions
Voltage detection
level
Power-on reset (POR)
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)*¹
Voltage detection circuit (LVD2)*²
Internal reset time Power-on reset (POR)
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Minimum VCC down time*³
Response delay time
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
V_POR
V_DET0
V_{DET1_8}
V_{DET1_9}
V_{DET1_A}
V_{DET2_8}
V_{DET2_9}
V_{DET2_A}
t_POR
t_LVO0
t_LVO1
t_LVO2
t_VOFF
t_DET
Td_(E-A)
V_LVH
2.46
2.7
2.75
2.70
2.73
2.75
2.70
2.73
200
2.58
2.82
2.90
2.85
2.88
2.90
2.85
2.88
9.7
9.7
0.9
0.9
—
80
2.7
2.94
3.05
3.00
3.03
3.05
3.00
3.03
—
200
3
V Figure 5.38
Figure 5.39
Figure 5.40
Figure 5.41
ms Figure 5.38
Figure 5.39
Figure 5.40
Figure 5.41
μs Figure 5.39 to
μs ^{Figure 5.41}
μs Figure 5.40,
mV ^{Figure 5.41}
Note 1. # in the symbol V_{DET1_#} denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note 2. # in the symbol V_{DET2 _#} denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR,
V_DET1, and V_DET2 for the POR/LVD.
Table 5.35 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Item
Symbol
Min.
Typ.
Max. Unit Test Conditions
Voltage detection Power-on reset (POR)
level
Voltage detection circuit (LVD0)
V_POR
3.6
3.8
4.0
V Figure 5.38
V_DET0
4.0
4.2
4.4
Figure 5.39
Voltage detection circuit (LVD1)*¹
V_{DET1_8}
4.59
4.77
4.95
Figure 5.40
V_{DET1_9}
4.05
4.23
4.41
V_{DET1_A}
4.32
4.50
4.68
Voltage detection circuit (LVD2)*²
V_{DET2_8}
4.59
4.77
4.95
Figure 5.41
V_{DET2_9}
4.05
4.23
4.41
V_{DET2_A}
4.32
4.50
4.68
Internal reset
time
Power-on reset (POR)
Voltage detection circuit (LVD0)
t_POR
t_LVO0
9.7
ms Figure 5.38
9.7
Figure 5.39
Voltage detection circuit (LVD1)
t_LVO1
0.9
Figure 5.40
Voltage detection circuit (LVD2)
t_LVO2
0.9
Figure 5.41
Minimum VCC down time*³
Response delay time
t_VOFF
200
—
—
μs Figure 5.39 to
t_DET
200
μs ^{Figure 5.43}
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
Td_(E-A)
V_LVH
3
μs Figure 5.40,
80
mV ^{Figure 5.41}
Note 1. # in the symbol V_{DET1_#} denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note 2. # in the symbol V_{DET2 _#} denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR,
V_DET1, and V_DET2 for the POR/LVD.
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
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