RX634 Datasheet, PDF (4/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 4)
Classification
Timers
Module/Function
Independent watchdog
timer (IWDTa)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
I²C bus interface (RIIC)
Serial peripheral
interface (RSPI)
CEC transmission/
reception circuit (CEC)
(3-V packages only)
Remote control signal
receiver (RCR)
(3-V packages only)
12-bit A/D converter (S12ADb)
D/A converter (DA)
CRC calculator (CRC)
Data Operation Circuit (DOC)
Operating frequency
Description
 14 bits  1 channel
 Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
 13 channels (channel 0 to 11: SCIe, channel 12: SCIf)
 Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB-first or MSB-first transfer
 Average transfer rate clock can be input from TMR timers (SCI5, SCI6, and SCI12)
 Simple IIC
 Simple SPI
 Master/slave mode supported (SCIf only)
 Start frame and information frame are included (SCIf only)
 3 channel
 Communications formats:
I²C bus format/SMBus format
 Master/slave selectable
 Max. transfer rate: Supports the fast mode (400 Kbps)
 2 channels
 Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or
clock-synchronous operation (three lines)
 Capable of handling serial transfer as a master or slave
 Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
 Double buffers for both transmission and reception
CEC signals can be generated and received conforming to the CEC standard, and communication
states can be detected by hardware.
 Serial communication can be performed conforming to the CEC standard.
 The operating clock can be selected from among the PCLK, main clock, and IWDTCLK.
 Any value can be set for the low-level width/bit width of the start bit and data bit during transmission
and reception.
 Errors and communication states can be detected by hardware.
 An error handling pulse can be output when a timing error of the long bit width is detected.
 Signal-free time can be counted.
 Receive operation can be restarted by detecting the start bit during reception.
 Two units
 Four pattern matching (header, data 0, data 1, and special data detection)
 8-byte receive buffer per unit
 The operating clock can be selected from among the PCLK, main clock, IWDTCLK, and TMR.
 12 bits (16 channels  1 unit)
 12-bit resolution
 Minimum conversion time: 1.0 s per channel (in operation with ADCLK at 50 MHz)
 Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
 Sample-and-hold function
 Self-diagnosis for the A/D converter
 Assistance in detecting disconnected analog inputs
 Double-trigger mode (duplication of A/D conversion data)
 A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
 2 channels
 10-bit resolution
 Output voltage: 0 V to VREFH
 CRC code generation for arbitrary amounts of data in 8-bit units
 Select any of three generating polynomials:
X⁸ + X² + X + 1, X¹⁶ + X¹⁵ + X² + 1, or X¹⁶ + X¹² + X⁵ + 1
 Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparison, addition, and subtraction of 16-bit data
54 MHz
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
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