RX634 Datasheet, PDF (82/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
Table 5.26 Timing of On-Chip Peripheral Modules (3)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Item
Symbol
Min.
Max.
Unit*¹
Test
Conditions
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
t_SPcyc
4
65536
t_Pcyc Figure 5.28
8
65536
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time
Data input hold time
SS input setup time
SS input hold time
Data output delay time
Data output hold time
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
t_SPCKWH
0.4
t_SPCKWL
0.4
t_SPCKr, t_SPCKf
—
t_SU
40
t_H
40
t_LEAD
6
t_LAG
6
t_OD
—
t_OH
–10
t_Dr, t_Df
—
t_SSLr, t_SSLf
—
t_SA
—
t_REL
—
0.6
t_SPcyc
0.6
t_SPcyc
20
ns
—
ns Figure 5.29 to
—
ns
Figure 5.34
—
t_Pcyc
—
t_Pcyc
40
ns
—
ns
20
ns
20
ns
5
t_Pcyc Figure 5.33,
5
t_Pcyc
Figure 5.34
Note 1. t_Pcyc: PCLKB cycle
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 82 of 106