RX634 Datasheet, PDF (9/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
1. Overview
1.4 Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1 / 4)
Classifications
Pin Name
Power supply
VCC
VCL
VSS
Clock
XTAL
EXTAL
BCLK
Clock frequency accuracy CACREF
measurement
Operating mode control MD
System control
RES#
EMLE
On-chip emulator
Address bus
Data bus
Multiplexed bus
Bus control
FINEC
FINED
TRST#
TMS
TDI
TCK
TDO
TRCLK
TRSYNC#
TRDATA0 to TRDATA3
A0 to A23
D0 to D15
A0/D0 to A15/D15
RD#
WR#
WR0# to WR1#
BC0# to BC1#
ALE
WAIT#
CS0# to CS3#
I/O
—
—
—
Output
Input
Output
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Output
Output
Output
Output
Output
I/O
I/O
Output
Output
Output
Output
Output
Input
Output
Description
Power supply pin. Connect this pin to the system power supply.
Connect the pin to VSS via a 0.1-μF multilayer ceramic capacitor.
The capacitor should be placed close to the pin.
Connect this pin to the VSS pin via the 0.1 μF smoothing capacitor
used to stabilize the internal power supply. Place the capacitor close
to the pin.
Ground pin. Connect it to the system power supply (0 V).
Pins for connecting a crystal resonator. An external clock signal can
be input through the EXTAL pin.
Outputs the external bus clock for external devices.
Input for the trigger signal in measuring accuracy of the clock
frequency
Pin for setting the operating mode. The signal levels on this pin
must not be changed during operation.
Reset pin. This MCU enters the reset state when this signal goes
low.
Input pin for the on-chip emulator enable signal. When the onchip
emulator is used, this pin should be driven high. When not used, it
should be driven low.
Fine interface clock pin
Fine interface pin
On-chip emulator pins. When the EMLE pin is driven high, these
pins are dedicated for the on-chip emulator.
This pin outputs the clock for synchronization with the trace data.
This pin indicates that output from the TRDATA0 to TRDATA3 pins
is valid.
These pins output the trace information.
Output pins for the address.
Input and output pins for the bidirectional data bus.
Address/data multiplexed bus
Strobe signal which indicates that reading from the external bus
interface space is in progress.
Strobe signal which indicates that writing to the external bus
interface space is in progress, in single-write strobe mode.
Strobe signals which indicate that either group of data bus pins (D7
to D0, and D15 to D8) is valid in writing to the external bus interface
space, in byte strobe mode.
Strobe signals which indicate that either group of data bus pins (D7
to D0 and D15 to D8) is valid in access to the external bus interface
space, in single-write strobe mode.
Address latch signal when address/data multiplexed bus is
selected.
Input pin for wait request signals in access to the external space.
Select signals for areas 0 to 3.
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 9 of 106