RX634 Datasheet, PDF (2/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
1. Overview
1.Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline.
Table 1.1
Outline of Specifications (1 / 4)
Classification
CPU
Module/Function
CPU
Memory
FPU
ROM
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection Voltage detection circuit
Low power
consumption
Interrupt
Low power consumption
facilities
Function for lower
operating power
consumption
Interrupt controller (ICUb)
Description
 Maximum operating frequency: 54 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system clock)
 Address space: 4-Gbyte linear
 Register
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
 Basic instructions: 73
 Floating-point instructions: 8
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32  32  64 bits
 Memory-protection unit (MPU)
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
 Capacity: 1 M/1.5 M/2 Mbytes
 54 MHz, no-wait memory access
 On-board programming: 3 types
Off-board programming
 Capacity: 128 Kbytes
 54 MHz, no-wait memory access
 Capacity: 32 Kbytes
 Number of times for programming/erasing: 100,000
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode
(software switching)
 Main clock oscillator, low-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated
on-chip oscillator
 Oscillation stop detection
 Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
 Independent settings for the system clock (ICLK), peripheral module clock (PCLKB), external bus
clock (BCLK), and FlashIF clock (FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 54 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLKB): 32 MHz (at
max.)
Devices connected to the external bus run in synchronization with the external bus clock (BCLK):
27 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FlashIF clock (FCLK): 32 MHz (at max.)
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, deep software standby reset, and software reset
 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
The detection voltage level of voltage detection circuit 0 is fixed
Voltage detection circuit 1 is capable of selecting the detection voltage from 3 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 3 levels
 Module stop function
 Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
 Operating power control modes
High-speed operating mode, low-speed operating mode 1, low-speed operating mode 2
 Interrupt vectors: 178
 External interrupts: 14 (NMI, IRQ0 to IRQ12 pins)
 Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, and IWDT interrupt)
 16 levels specifiable for the order of priority
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 2 of 106