RX634 Datasheet, PDF (83/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
Table 5.27 Timing of On-Chip Peripheral Modules (4)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Item
Symbol
Min.⁽*^1, *²⁾
Max.
Test
Unit Conditions
RIIC
SCL input cycle time
(Standard-mode) _{SCL input high pulse width}
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
RIIC
(Fast-mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
6 (12) × t_IICcyc + 1300
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
—
—
—
—
1000
—
300
0
3 (6) × t_IICcyc + 300
t_IICcyc + 300
1000
1 (4) × t_IICcyc
—
—
—
1000
—
t_IICcyc + 50
—
0
—
—
400
6 (12) × t_IICcyc + 600
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
20 + 0.1C_b
20 + 0.1C_b
0
3 (6) × t_IICcyc + 300
t_IICcyc + 300
300
—
—
—
300
300
1 (4) × t_IICcyc
—
—
—
300
—
t_IICcyc + 50
—
0
—
—
400
ns Figure 5.35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Note:
Note 1.
Note 2.
t_IICcyc: RIIC internal reference count clock (IICφ) cycle
The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bits = 1.
C_b indicates the total capacity of the bus line.
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 83 of 106