RX634 Datasheet, PDF (81/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
Table 5.25 Timing of On-Chip Peripheral Modules (2)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Item
Symbol
Min.
RSPI RSPCK clock cycle
Master
Slave
t_SPcyc
2
8
RSPCK clock high
pulse width
Master
Slave
RSPCK clock low
pulse width
Master
Slave
RSPCK clock rise/
fall time
Output
Input
t_SPCKWH (t_SPcyc – t_SPCKr –
t_SPCKf)/2 – 3
(t_SPcyc – t_SPCKr –
t_SPCKf)/2
t_SPCKWL (t_SPcyc – t_SPCKr–
t_SPCKf)/2 – 3
(t_SPcyc – t_SPCKr –
t_SPCKf)/2
t_SPCKr,
—
t_SPCKf
—
Data input setup time Master
t_SU
Slave
Data input hold time Master PCLKB set to a
t_H
division ratio other
than divided by 2
15
20 – t_Pcyc
t_Pcyc
PCLKB set to
0
divided by 2
SSL setup time
Slave
Master
Slave
t_LEAD
20 + 2 × t_Pcyc
1
4
SSL hold time
Master
Slave
t_LAG
1
4
Data output delay
time
Master
Slave
t_OD
—
—
Data output hold time Master
Slave
t_OH
0
0
Successive
transmission delay
time
Master
Slave
MOSI and MISO rise/ Output
fall time
Input
t_TD
t_SPcyc + 2 × t_Pcyc
t_Dr, t_Df
4 × t_Pcyc
—
—
SSL rise/fall time
Output
Input
t_SSLr,
—
t_SSLf
—
Slave access time
Slave output release time
t_SA
—
t_REL
—
Max.
4096
4096
—
—
—
—
5
1
—
—
—
—
—
8
—
8
—
18
3 × t_Pcyc + 40
—
—
8 × t_SPcyc + 2 ×
t_Pcyc
—
5
1
5
1
4
3
Test
Unit*¹ Conditions
t_Pcyc Figure 5.28
ns
ns
ns
μs
ns Figure 5.29 to
Figure 5.34
ns
t_SPcyc
t_Pcyc
t_SPcyc
t_Pcyc
ns
ns
ns
ns
μs
ns
μs
t_Pcyc Figure 5.33,
t_Pcyc ^{Figure 5.34}
Note 1. t_Pcyc: PCLKB cycle
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 81 of 106