RX634 Datasheet, PDF (43/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (18 / 34)
Address
0008 8603h
0008 8604h
0008 8605h
0008 8606h
0008 8607h
0008 8608h
0008 8609h
0008 860Ah
0008 860Dh
0008 860Eh
0008 860Fh
0008 8610h
0008 8612h
0008 8614h
0008 8616h
0008 8618h
0008 861Ah
0008 861Ch
0008 861Eh
0008 8620h
0008 8622h
0008 8624h
0008 8626h
0008 8628h
0008 862Ah
0008 862Ch
0008 862Dh
0008 8630h
0008 8631h
0008 8632h
0008 8634h
0008 8636h
0008 8638h
Module
Symbol
MTU4
MTU3
MTU3
MTU4
MTU4
MTU3
MTU4
MTU
MTU
MTU
MTU
MTU3
MTU4
MTU
MTU
MTU3
MTU3
MTU4
MTU4
MTU
MTU
MTU3
MTU3
MTU4
MTU4
MTU3
MTU4
MTU
MTU
MTU
MTU
MTU
MTU3
0008 8639h MTU4
0008 8640h MTU4
0008 8644h MTU4
0008 8646h MTU4
0008 8648h MTU4
0008 864Ah MTU4
0008 8660h
0008 8680h
0008 8681h
0008 8684h
0008 8690h
0008 8691h
0008 8692h
0008 8693h
MTU
MTU
MTU
MTU
MTU0
MTU1
MTU2
MTU3
Register Name
Register
Symbol
Timer Mode Register
TMDR
Timer I/O Control Register H
TIORH
Timer I/O Control Register L
TIORL
Timer I/O Control Register H
TIORH
Timer I/O Control Register L
TIORL
Timer Interrupt Enable Register
TIER
Timer Interrupt Enable Register
TIER
Timer Output Master Enable Register
TOER
Timer Gate Control Register
TGCR
Timer Output Control Register 1
TOCR1
Timer Output Control Register 2
TOCR2
Timer Counter
TCNT
Timer Counter
TCNT
Timer Cycle Data Register
TCDR
Timer Dead Time Data Register
TDDR
Timer General Register A
TGRA
Timer General Register B
TGRB
Timer General Register A
TGRA
Timer General Register B
TGRB
Timer Subcounter
TCNTS
Timer Cycle Buffer Register
TCBR
Timer General Register C
TGRC
Timer General Register D
TGRD
Timer General Register C
TGRC
Timer General Register D
TGRD
Timer Status Register
TSR
Timer Status Register
TSR
Timer Interrupt Skipping Set Register
TITCR
Timer Interrupt Skipping Counter
TITCNT
Timer Buffer Transfer Set Register
TBTER
Timer Dead Time Enable Register
TDER
Timer Output Level Buffer Register
TOLBR
Timer Buffer Operation Transfer Mode
Register
TBTM
Timer Buffer Operation Transfer Mode
Register
TBTM
Timer A/D Converter Start Request
Control Register
TADCR
Timer A/D Converter Start Request Cycle TADCORA
Set Register A
Timer A/D Converter Start Request Cycle TADCORB
Set Register B
Timer A/D Converter Start Request Cycle TADCOBRA
Set Buffer Register A
Timer A/D Converter Start Request Cycle TADCOBRB
Set Buffer Register B
Timer Waveform Control Register
TWCR
Timer Start Register
TSTR
Timer Synchronous Register
TSYR
Timer Read/Write Enable Register
TRWER
Noise Filter Control Register
NFCR
Noise Filter Control Register
NFCR
Noise Filter Control Register
NFCR
Noise Filter Control Register
NFCR
Number
of Bits
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
Access
Size
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
Number of Access Cycles
ICLK ≥
PCLK
ICLK <
PCLK
Related
Function
2 to 3PCLKB 2 ICLK MTU2a
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
16
16
2 to 3PCLKB 2 ICLK
16
16
2 to 3PCLKB 2 ICLK
16
16
2 to 3PCLKB 2 ICLK
16
16
2 to 3PCLKB 2 ICLK
16
16
2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
8
8, 16 2 to 3PCLKB 2 ICLK
Remarks
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 43 of 106