RX634 Datasheet, PDF (84/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
Table 5.28 Timing of On-Chip Peripheral Modules (5)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Item
Symbol Min.⁽*^1, *²⁾
Max.*³
Test
Unit Conditions
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
—
—
0
250
0
—
20 + 0.1C_b
20 + 0.1C_b
0
100
0
—
1000
300
4 × t_pcyc
—
—
400
300
300
4 × t_pcyc
—
—
400
ns Figure 5.35
ns
ns
ns
ns
pF
ns
ns
ns
ns
ns
pF
Note 1.
Note 2.
Note 3.
The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bits = 1.
C_b indicates the total capacity of the bus line.
t_Pcyc: PCLKB cycle
Table 5.29 Timing of On-Chip Peripheral Modules (6)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
Item
CEC fall time
Symbol
t_cf
Min.
—
Max.
50
Unit
μs
Test Conditions
C_b = 1600 pF, R_b = 27 kΩ
C_b = 7700 pF, R_b = 3 kΩ
Note 1. Cb: Communication line load capacitance; Rb: Communication line external pull-up resistance
PCLKB
Port
t_PRW
Figure 5.20 I/O Port Input Timing
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 84 of 106