RX634 Datasheet, PDF (51/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (26 / 34)
Address
0008 C00Ah
0008 C00Bh
0008 C00Ch
0008 C00Dh
0008 C00Eh
0008 C00Fh
0008 C011h
0008 C012h
0008 C013h
0008 C014h
0008 C020h
0008 C021h
0008 C022h
0008 C023h
0008 C025h
0008 C026h
0008 C027h
0008 C028h
0008 C029h
0008 C02Ah
0008 C02Bh
0008 C02Ch
0008 C02Dh
0008 C02Eh
0008 C02Fh
0008 C031h
0008 C032h
0008 C033h
0008 C034h
0008 C040h
0008 C041h
0008 C042h
0008 C043h
0008 C044h
0008 C045h
0008 C046h
0008 C047h
0008 C048h
0008 C049h
0008 C04Ah
0008 C04Bh
0008 C04Ch
0008 C04Dh
0008 C04Eh
0008 C04Fh
0008 C051h
0008 C052h
0008 C053h
0008 C054h
0008 C060h
0008 C061h
Module
Symbol
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTH
PORTJ
PORTK
PORTL
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT7
PORT8
PORT9
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTH
PORTJ
PORTK
PORTL
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTH
PORTJ
PORTK
PORTL
PORT0
PORT1
Register Name
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Direction Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Output Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Input Data Register
Port Mode Register
Port Mode Register
Register
Symbol
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PMR
PMR
Number
of Bits
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Access
Size
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Number of Access Cycles
ICLK ≥
PCLK
ICLK <
PCLK
Related
Function
2 to 3PCLKB 2 ICLK I/O Ports
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
Remarks
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 51 of 106