RX634 Datasheet, PDF (3/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 4)
Classification Module/Function
External bus extension
DMA
DMA controller (DMACA)
I/O ports
Data transfer controller
(DTCa)
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
16-bit timer pulse unit
(TPUa)
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Programmable pulse
generator (PPG)
8-bit timer (TMR)
Compare match timer
(CMT)
Watchdog timer (WDTA)
Description
 The external address space can be divided into four areas (CS0 to CS3), each with independent
control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8-bit or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
 Wait control
 Write buffer facility
 4 channels
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Interrupts
 Chain transfer function
144-pin
 I/O: 114
 Input: 9 (P40 to P47, P35)
 Pull-up resistors: 111
 Open-drain outputs: 114
 5-V tolerance: Not supported
 Event signals of 56 types can be directly connected to the module
 Operations of timer modules are selectable at event input
 Capable of event link operation for ports B and E
 Capable of selecting input/output function from multiple pins
 (16 bits × 6 channels) × 1 unit
 Maximum of 16 pulse-input/output possible
 Select from among seven or eight counter-input clock signals for each channel
 Supports the input capture/output compare function
 Output of PWM waveforms in up to 15 phases in PWM mode
 Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade-
connected operation (32 bits × 2 channels) depending on the channel.
 Capable of generating conversion start triggers for the A/D converters
 Signals from the input capture pins are input via a digital filter
 (16 bits  6 channels)  1 unit
 Up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer
channels
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 21 output compare/input capture registers
 Pulse output mode
 Complementary PWM output mode
 Reset synchronous PWM mode
 Phase-counting mode
 Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
 (4 bits  4 groups)  1 unit
 Pulse output with the MTU output as a trigger
 Maximum of 16 pulse-output possible
 (8 bits  2 channels)  2 units
 Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
 Capable of output of pulse trains with desired duty cycles or of PWM signals
 The 2 channels of each unit can be cascaded to create a 16-bit timer
 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
 Capable of generating a receive clock for the RCR
 (16 bits  2 channels)  2 units
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits  1 channel
 Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,
PCLK/2048, PCLK/8192)
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
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